Attention is currently required from: Jamie Ryu, Harsha B R, Sridhar Siricilla, Usha P, Eric Lai.

Harsha B R uploaded patch set #2 to this change.

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mb/intel/mtlrvp: Enable GSPI interface

This patch enables GSPI [1] interface for mtlrvp based on mtlrvp
schematics.

BUG=b:224325352
BRANCH=None
TEST=Able to observe corresponding UPD configuration with FSP dump and
able to boot mtlrvp (LP5/DDR5) to ChromeOS.
SPI[0].Mode                 = 0
SPI[0].DefaultCsOutput      = 0
SPI[0].CsMode               = 0
SPI[0].CsState              = 0
SPI[1].Mode                 = 1
SPI[1].DefaultCsOutput      = 0
SPI[1].CsMode               = 0
SPI[1].CsState              = 0

Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: I3d4c4f19dd80fefa80c365b5ecac0a234f5af860
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
---
M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
1 file changed, 43 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/72706/2

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