Attention is currently required from: Hung-Te Lin, Ryan Chuang, Yu-Ping Wu.

Rex-BC Chen uploaded patch set #2 to this change.

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vc/mediatek/mt8195: Enable VREF calibration at DDR3200 for enter/exit S0 stability

Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: I9df776b393f6b6166d1d6f02d5e96bd7ebc4a707
---
M src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/56105/2

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