Tongtong Pan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85320?usp=email )
Change subject: mb/google/fatcat/var/felino: Add initial memory config ......................................................................
mb/google/fatcat/var/felino: Add initial memory config
Configure memory according to schematics revision 20241120.
BUG=b:379797598 TEST=abuild -v -a -x -c max -p none -t google/fatcat -b felino
Change-Id: I8420c5cf0421ec9265613c3e1374542a067ce6ed Signed-off-by: Tongtong Pan pantongtong@huaqin.corp-partner.google.com --- A src/mainboard/google/fatcat/variants/felino/memory.c M src/mainboard/google/fatcat/variants/felino/memory/Makefile.mk M src/mainboard/google/fatcat/variants/felino/memory/dram_id.generated.txt M src/mainboard/google/fatcat/variants/felino/memory/mem_parts_used.txt 4 files changed, 81 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/85320/1
diff --git a/src/mainboard/google/fatcat/variants/felino/memory.c b/src/mainboard/google/fatcat/variants/felino/memory.c new file mode 100644 index 0000000..e0908ad --- /dev/null +++ b/src/mainboard/google/fatcat/variants/felino/memory.c @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <soc/romstage.h> +#include <soc/meminit.h> + +static const struct mb_cfg lp5_mem_config = { + .type = MEM_TYPE_LP5X, + + .lpx_dq_map = { + .ddr0 = { + .dq0 = { 13, 14, 12, 15, 11, 10, 8, 9, }, + .dq1 = { 7, 5, 4, 6, 0, 3, 1, 2 }, + }, + .ddr1 = { + .dq0 = { 1, 3, 0, 2, 7, 4, 6, 5, }, + .dq1 = { 12, 13, 14, 15, 11, 10, 9, 8 }, + }, + .ddr2 = { + .dq0 = { 0, 2, 1, 3, 6, 4, 7, 5 }, + .dq1 = { 14, 13, 15, 12, 8, 11, 10, 9, }, + }, + .ddr3 = { + .dq0 = { 6, 5, 7, 4, 2, 3, 1, 0, }, + .dq1 = { 10, 8, 11, 9, 12, 15, 13, 14 }, + }, + .ddr4 = { + .dq0 = { 2, 1, 3, 0, 4, 7, 5, 6 }, + .dq1 = { 15, 14, 12, 13, 9, 11, 10, 8, }, + }, + .ddr5 = { + .dq0 = { 6, 5, 7, 4, 3, 1, 0, 2, }, + .dq1 = { 10, 9, 11, 8, 13, 14, 12, 15 }, + }, + .ddr6 = { + .dq0 = { 9, 10, 11, 8, 14, 12, 13, 15, }, + .dq1 = { 0, 1, 2, 3, 5, 7, 4, 6 }, + }, + .ddr7 = { + .dq0 = { 0, 1, 2, 3, 7, 5, 6, 4, }, + .dq1 = { 14, 13, 15, 12, 10, 8, 11, 9 }, + }, + }, + + .lpx_dqs_map = { + .ddr0 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr6 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr7 = { .dqs0 = 0, .dqs1 = 1 } + }, + + .ect = true, /* Early Command Training */ + + .lp_ddr_dq_dqs_re_training = 1, + + .user_bd = BOARD_TYPE_ULT_ULX, + + .lp5x_config = { + .ccc_config = 0xFF, + }, +}; + +const struct mb_cfg *variant_memory_params(void) +{ + return &lp5_mem_config; +} + +void variant_get_spd_info(struct mem_spd *spd_info) +{ + spd_info->topo = MEM_TOPO_MEMORY_DOWN; + spd_info->cbfs_index = 0; +} diff --git a/src/mainboard/google/fatcat/variants/felino/memory/Makefile.mk b/src/mainboard/google/fatcat/variants/felino/memory/Makefile.mk index 62c45356..e5e7db7 100644 --- a/src/mainboard/google/fatcat/variants/felino/memory/Makefile.mk +++ b/src/mainboard/google/fatcat/variants/felino/memory/Makefile.mk @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# util/spd_tools/bin/part_id_gen ptl lp5 src/mainboard/google/fatcat/variants/francka/memory/ src/mainboard/google/fatcat/variants/francka/memory/mem_parts_used.txt +# util/spd_tools/bin/part_id_gen ptl lp5 src/mainboard/google/fatcat/variants/felino/memory/ src/mainboard/google/fatcat/variants/felino/memory/mem_parts_used.txt
SPD_SOURCES = -SPD_SOURCES += spd/lp5/set-0/spd-10.hex # ID = 0(0b0000) Parts = MT62F2G32D4DS-020 WT:F +SPD_SOURCES += spd/lp5/set-0/spd-11.hex # ID = 0(0b0000) Parts = MT62F1G32D2DS-023 WT:C diff --git a/src/mainboard/google/fatcat/variants/felino/memory/dram_id.generated.txt b/src/mainboard/google/fatcat/variants/felino/memory/dram_id.generated.txt index 31165c4..c7f7a38 100644 --- a/src/mainboard/google/fatcat/variants/felino/memory/dram_id.generated.txt +++ b/src/mainboard/google/fatcat/variants/felino/memory/dram_id.generated.txt @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# util/spd_tools/bin/part_id_gen ptl lp5 src/mainboard/google/fatcat/variants/francka/memory/ src/mainboard/google/fatcat/variants/francka/memory/mem_parts_used.txt +# util/spd_tools/bin/part_id_gen ptl lp5 src/mainboard/google/fatcat/variants/felino/memory/ src/mainboard/google/fatcat/variants/felino/memory/mem_parts_used.txt
DRAM Part Name ID to assign -MT62F2G32D4DS-020 WT:F 0 (0000) +MT62F1G32D2DS-023 WT:C 0 (0000) diff --git a/src/mainboard/google/fatcat/variants/felino/memory/mem_parts_used.txt b/src/mainboard/google/fatcat/variants/felino/memory/mem_parts_used.txt index e6822f6..971c5fb 100644 --- a/src/mainboard/google/fatcat/variants/felino/memory/mem_parts_used.txt +++ b/src/mainboard/google/fatcat/variants/felino/memory/mem_parts_used.txt @@ -9,4 +9,4 @@ # See util/spd_tools/README.md for more details and instructions.
# Part Name -MT62F2G32D4DS-020 WT:F +MT62F1G32D2DS-023 WT:C