Patch Set 1: Code-Review-1
Dug a little into the chipset support for historical Intel
in the tree: Older ICHs implement the bit r/w but mention
to ignore it anyway, because everything goes to PCI. So that
should be fine.
440BX doesn't seem to know it, though :-/ So this can't go
in as is. I'm open for suggestions. What should we do if
16-bit decode isn't possible? Restrict all i/o to 10 bits?
That could brick... Hmmmm, just warn about it? Instead of
skipping the device?
I really don't like to reserve the VGA resources 64 times,
could do that, though.
Patch Set #1, Line 174:
#define PCI_CB_BRIDGE_CTL_VGA 0x08
Not sure what 0x10 is with cardbus. […]
cardbus matches, see spec
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