1 comment:
File src/mainboard/google/drallion/romstage.c:
spd[0] = {
.read_type = READ_SMBUS,
.spd_spec = {.spd_smbus_address = 0xa0},
},
.spd[1] = {.read_type = NOT_EXISTING},
.spd[2] = {
.read_type = READ_SMBUS,
.spd_spec = {.spd_smbus_address = 0xa4},
},
.spd[3] = {.read_type = NOT_EXISTING},
Also, this will have to be updated based on GPP_F1 and GPP_F2?
No, as I said, this currently copy from Sarien and we will remove this in Drallion, we only use on-board ram and use the SPD files by CBFS.
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