Jian Tong has uploaded this change for review.

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mb/google/brox/var/lotso: Fine tune I2C frequency

I2C0 - 392kHz
I2C5 - 400kHz

BUG=b:349747500,b:349735055
TEST=emerge-brox sys-boot/coreboot

Change-Id: I985837b1b80e973f148529b446905580c0f95e98
Signed-off-by: Jing Tong <tongjian@huaqin.corp-partner.google.com>
---
M src/mainboard/google/brox/variants/lotso/overridetree.cb
1 file changed, 16 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/83290/1

diff --git a/src/mainboard/google/brox/variants/lotso/overridetree.cb b/src/mainboard/google/brox/variants/lotso/overridetree.cb
index 274e22c..187840f 100644
--- a/src/mainboard/google/brox/variants/lotso/overridetree.cb
+++ b/src/mainboard/google/brox/variants/lotso/overridetree.cb
@@ -48,6 +48,22 @@
 	register "tcss_ports[0]" = "TCSS_PORT_EMPTY"	# Disable TCP0
 	register "tcss_ports[2]" = "TCSS_PORT_EMPTY" 	# Disable TCP2
 
+	register "common_soc_config" = "{
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 650,
+			.fall_time_ns = 350,
+			.data_hold_time_ns = 400,
+		},
+		.i2c[4] = {
+			.early_init = 1,
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 600,
+			.fall_time_ns = 110,
+			.data_hold_time_ns = 100,
+		},
+	}"
+
 	register "serial_io_gspi_mode" = "{
 		[PchSerialIoIndexGSPI0] = PchSerialIoPci,
 		[PchSerialIoIndexGSPI1] = PchSerialIoPci,

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