Name of user not set #1002723 has uploaded this change for review.
screen fix
Change-Id: Ie68e77af77ccec83c29d3329ee9997b950b351f6
---
A grub.cfg
A src/mainboard/dell/Kconfig
A src/mainboard/dell/Kconfig.name
A src/mainboard/dell/dell_system_vostro_3360/Kconfig
A src/mainboard/dell/dell_system_vostro_3360/Kconfig.name
A src/mainboard/dell/dell_system_vostro_3360/Makefile.inc
A src/mainboard/dell/dell_system_vostro_3360/acpi/ec.asl
A src/mainboard/dell/dell_system_vostro_3360/acpi/platform.asl
A src/mainboard/dell/dell_system_vostro_3360/acpi/superio.asl
A src/mainboard/dell/dell_system_vostro_3360/acpi_tables.c
A src/mainboard/dell/dell_system_vostro_3360/board_info.txt
A src/mainboard/dell/dell_system_vostro_3360/devicetree.cb
A src/mainboard/dell/dell_system_vostro_3360/dsdt.asl
A src/mainboard/dell/dell_system_vostro_3360/early_init.c
A src/mainboard/dell/dell_system_vostro_3360/gma-mainboard.ads
A src/mainboard/dell/dell_system_vostro_3360/gpio.c
A src/mainboard/dell/dell_system_vostro_3360/hda_verb.c
A src/mainboard/dell/dell_system_vostro_3360/mainboard.c
M util/superiotool/ite.c
A util/superiotool/output
20 files changed, 1,275 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/39172/1
diff --git a/grub.cfg b/grub.cfg
new file mode 100644
index 0000000..0e941ec
--- /dev/null
+++ b/grub.cfg
@@ -0,0 +1 @@
+configfile (ahci0,3)/boot/grub/grub.cfg
diff --git a/src/mainboard/dell/Kconfig b/src/mainboard/dell/Kconfig
new file mode 100755
index 0000000..298c62b
--- /dev/null
+++ b/src/mainboard/dell/Kconfig
@@ -0,0 +1,16 @@
+if VENDOR_DELL
+
+choice
+ prompt "Mainboard model"
+
+source "src/mainboard/dell/*/Kconfig.name"
+
+endchoice
+
+source "src/mainboard/dell/*/Kconfig"
+
+config MAINBOARD_VENDOR
+ string
+ default "Dell Inc."
+
+endif # VENDOR_DELL
diff --git a/src/mainboard/dell/Kconfig.name b/src/mainboard/dell/Kconfig.name
new file mode 100755
index 0000000..3d2fefd
--- /dev/null
+++ b/src/mainboard/dell/Kconfig.name
@@ -0,0 +1,2 @@
+config VENDOR_DELL
+ bool "Dell Inc."
diff --git a/src/mainboard/dell/dell_system_vostro_3360/Kconfig b/src/mainboard/dell/dell_system_vostro_3360/Kconfig
new file mode 100755
index 0000000..8861897
--- /dev/null
+++ b/src/mainboard/dell/dell_system_vostro_3360/Kconfig
@@ -0,0 +1,43 @@
+if BOARD_DELL_DELL_SYSTEM_VOSTRO_3360
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ROMSIZE_KB_8192
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select INTEL_INT15
+ select GFX_GMA_INTERNAL_IS_LVDS
+ select MAINBOARD_HAS_LIBGFXINIT # FIXME: check this
+ select NORTHBRIDGE_INTEL_SANDYBRIDGE
+ select SERIRQ_CONTINUOUS_MODE
+ select SOUTHBRIDGE_INTEL_C216
+ select USE_NATIVE_RAMINIT
+
+config MAINBOARD_DIR
+ string
+ default dell/dell_system_vostro_3360
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Dell System Vostro 3360"
+
+config VGA_BIOS_FILE
+ string
+ default "pci8086,0156.rom"
+
+config VGA_BIOS_ID
+ string
+ default "8086,0156"
+
+config DRAM_RESET_GATE_GPIO # FIXME: check this
+ int
+ default 60
+
+config MAX_CPUS
+ int
+ default 8
+
+config USBDEBUG_HCD_INDEX # FIXME: check this
+ int
+ default 2
+endif
diff --git a/src/mainboard/dell/dell_system_vostro_3360/Kconfig.name b/src/mainboard/dell/dell_system_vostro_3360/Kconfig.name
new file mode 100755
index 0000000..8925217
--- /dev/null
+++ b/src/mainboard/dell/dell_system_vostro_3360/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_DELL_DELL_SYSTEM_VOSTRO_3360
+ bool "Dell System Vostro 3360"
diff --git a/src/mainboard/dell/dell_system_vostro_3360/Makefile.inc b/src/mainboard/dell/dell_system_vostro_3360/Makefile.inc
new file mode 100755
index 0000000..18391d8
--- /dev/null
+++ b/src/mainboard/dell/dell_system_vostro_3360/Makefile.inc
@@ -0,0 +1,5 @@
+bootblock-y += early_init.c
+bootblock-y += gpio.c
+romstage-y += early_init.c
+romstage-y += gpio.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/dell/dell_system_vostro_3360/acpi/ec.asl b/src/mainboard/dell/dell_system_vostro_3360/acpi/ec.asl
new file mode 100755
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/dell/dell_system_vostro_3360/acpi/ec.asl
diff --git a/src/mainboard/dell/dell_system_vostro_3360/acpi/platform.asl b/src/mainboard/dell/dell_system_vostro_3360/acpi/platform.asl
new file mode 100755
index 0000000..afb8abb
--- /dev/null
+++ b/src/mainboard/dell/dell_system_vostro_3360/acpi/platform.asl
@@ -0,0 +1,8 @@
+Method(_WAK, 1)
+{
+ Return(Package() {0, 0})
+}
+
+Method(_PTS, 1)
+{
+}
diff --git a/src/mainboard/dell/dell_system_vostro_3360/acpi/superio.asl b/src/mainboard/dell/dell_system_vostro_3360/acpi/superio.asl
new file mode 100755
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/dell/dell_system_vostro_3360/acpi/superio.asl
diff --git a/src/mainboard/dell/dell_system_vostro_3360/acpi_tables.c b/src/mainboard/dell/dell_system_vostro_3360/acpi_tables.c
new file mode 100755
index 0000000..cfc2061
--- /dev/null
+++ b/src/mainboard/dell/dell_system_vostro_3360/acpi_tables.c
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/bd82x6x/nvs.h>
+
+/* FIXME: check this function. */
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ /* Disable USB ports in S3 by default */
+ gnvs->s3u0 = 0;
+ gnvs->s3u1 = 0;
+
+ /* Disable USB ports in S5 by default */
+ gnvs->s5u0 = 0;
+ gnvs->s5u1 = 0;
+
+ /* The lid is open by default. */
+ gnvs->lids = 1;
+
+ gnvs->tcrt = 100;
+ gnvs->tpsv = 90;
+}
diff --git a/src/mainboard/dell/dell_system_vostro_3360/board_info.txt b/src/mainboard/dell/dell_system_vostro_3360/board_info.txt
new file mode 100755
index 0000000..be6bff8
--- /dev/null
+++ b/src/mainboard/dell/dell_system_vostro_3360/board_info.txt
@@ -0,0 +1,4 @@
+Category: desktop
+ROM protocol: SPI
+Flashrom support: n
+FIXME: check category, , put ROM package, ROM socketed, Release year
diff --git a/src/mainboard/dell/dell_system_vostro_3360/devicetree.cb b/src/mainboard/dell/dell_system_vostro_3360/devicetree.cb
new file mode 100755
index 0000000..d234325
--- /dev/null
+++ b/src/mainboard/dell/dell_system_vostro_3360/devicetree.cb
@@ -0,0 +1,111 @@
+chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
+ register "gfx.link_frequency_270_mhz" = "1"
+ register "gfx.use_spread_spectrum_clock" = "1"
+ register "gpu_cpu_backlight" = "0x00001312"
+ register "gpu_dp_b_hotplug" = "4"
+ register "gpu_dp_c_hotplug" = "4"
+ register "gpu_dp_d_hotplug" = "4"
+ register "gpu_panel_port_select" = "0"
+ register "gpu_panel_power_backlight_off_delay" = "3000"
+ register "gpu_panel_power_backlight_on_delay" = "1700"
+ register "gpu_panel_power_cycle_delay" = "5"
+ register "gpu_panel_power_down_delay" = "300"
+ register "gpu_panel_power_up_delay" = "300"
+ register "gpu_pch_backlight" = "0x13121312"
+ device cpu_cluster 0x0 on
+ chip cpu/intel/model_206ax # FIXME: check all registers
+ register "c1_acpower" = "1"
+ register "c1_battery" = "1"
+ register "c2_acpower" = "3"
+ register "c2_battery" = "3"
+ register "c3_acpower" = "5"
+ register "c3_battery" = "5"
+ device lapic 0x0 on
+ end
+ device lapic 0xacac off
+ end
+ end
+ end
+ device domain 0x0 on
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+ register "c2_latency" = "0x0065"
+ register "docking_supported" = "1"
+ register "gen1_dec" = "0x00040069"
+ register "gen2_dec" = "0x00040911"
+ register "gen3_dec" = "0x00000000"
+ register "gen4_dec" = "0x000c06a1"
+ register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
+ register "pcie_port_coalesce" = "1"
+ register "sata_interface_speed_support" = "0x3"
+ register "sata_port_map" = "0x1"
+ register "spi_lvscc" = "0x2005"
+ register "spi_uvscc" = "0x2005"
+ register "superspeed_capable_ports" = "0x0000000f"
+ register "xhci_overcurrent_mapping" = "0x00000c03"
+ register "xhci_switchable_ports" = "0x0000000f"
+ device pci 14.0 on # USB 3.0 Controller
+ subsystemid 0x1028 0x055c
+ end
+ device pci 16.0 off # Management Engine Interface 1
+ end
+ device pci 16.1 off # Management Engine Interface 2
+ end
+ device pci 16.2 off # Management Engine IDE-R
+ end
+ device pci 16.3 off # Management Engine KT
+ end
+ device pci 19.0 off # Intel Gigabit Ethernet
+ end
+ device pci 1a.0 on # USB2 EHCI #2
+ subsystemid 0x1028 0x055c
+ end
+ device pci 1b.0 on # High Definition Audio
+ subsystemid 0x1028 0x055c
+ end
+ device pci 1c.0 on # PCIe Port #1
+ subsystemid 0x1028 0x055c
+ end
+ device pci 1c.1 off # PCIe Port #2
+ end
+ device pci 1c.2 off # PCIe Port #3
+ end
+ device pci 1c.3 off # PCIe Port #4
+ end
+ device pci 1c.4 on # PCIe Port #5
+ subsystemid 0x1028 0x055c
+ end
+ device pci 1c.5 off # PCIe Port #6
+ end
+ device pci 1c.6 off # PCIe Port #7
+ end
+ device pci 1c.7 off # PCIe Port #8
+ end
+ device pci 1d.0 on # USB2 EHCI #1
+ subsystemid 0x1028 0x055c
+ end
+ device pci 1e.0 off # PCI bridge
+ end
+ device pci 1f.0 on # LPC bridge PCI-LPC bridge
+ subsystemid 0x1028 0x055c
+ end
+ device pci 1f.2 on # SATA Controller 1
+ subsystemid 0x1028 0x055c
+ end
+ device pci 1f.3 on # SMBus
+ subsystemid 0x1028 0x055c
+ end
+ device pci 1f.5 off # SATA Controller 2
+ end
+ device pci 1f.6 off # Thermal
+ end
+ end
+ device pci 00.0 on # Host bridge Host bridge
+ subsystemid 0x1028 0x055c
+ end
+ device pci 01.0 off # PEG
+ end
+ device pci 02.0 on # iGPU
+ subsystemid 0x1028 0x055c
+ end
+ end
+end
diff --git a/src/mainboard/dell/dell_system_vostro_3360/dsdt.asl b/src/mainboard/dell/dell_system_vostro_3360/dsdt.asl
new file mode 100755
index 0000000..b00a7ff
--- /dev/null
+++ b/src/mainboard/dell/dell_system_vostro_3360/dsdt.asl
@@ -0,0 +1,29 @@
+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
+#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
+
+
+#include <arch/acpi.h>
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, /* DSDT revision: ACPI 2.0 and up */
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20141018 /* OEM revision */
+)
+{
+ #include "acpi/platform.asl"
+ #include <cpu/intel/common/acpi/cpu.asl>
+ #include <southbridge/intel/common/acpi/platform.asl>
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
+
+ Device (\_SB.PCI0)
+ {
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
+ }
+}
diff --git a/src/mainboard/dell/dell_system_vostro_3360/early_init.c b/src/mainboard/dell/dell_system_vostro_3360/early_init.c
new file mode 100755
index 0000000..6dbf226
--- /dev/null
+++ b/src/mainboard/dell/dell_system_vostro_3360/early_init.c
@@ -0,0 +1,64 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* FIXME: Check if all includes are needed. */
+
+#include <stdint.h>
+#include <string.h>
+#include <timestamp.h>
+#include <arch/byteorder.h>
+#include <device/mmio.h>
+#include <device/pci_ops.h>
+#include <device/pnp_ops.h>
+#include <console/console.h>
+#include <bootblock_common.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/gpio.h>
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ { 1, 1, 0 },
+ { 1, 1, 0 },
+ { 1, 1, 1 },
+ { 1, 1, 1 },
+ { 1, 1, 2 },
+ { 1, 1, 2 },
+ { 0, 1, 3 },
+ { 0, 1, 3 },
+ { 1, 1, 4 },
+ { 0, 1, 4 },
+ { 1, 1, 5 },
+ { 0, 1, 5 },
+ { 1, 1, 6 },
+ { 0, 1, 6 },
+};
+
+void bootblock_mainboard_early_init(void)
+{
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
+}
+
+/* FIXME: Put proper SPD map here. */
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+ read_spd(&spd[0], 0x50, id_only);
+ read_spd(&spd[1], 0x51, id_only);
+ read_spd(&spd[2], 0x52, id_only);
+ read_spd(&spd[3], 0x53, id_only);
+}
diff --git a/src/mainboard/dell/dell_system_vostro_3360/gma-mainboard.ads b/src/mainboard/dell/dell_system_vostro_3360/gma-mainboard.ads
new file mode 100755
index 0000000..d7afe73
--- /dev/null
+++ b/src/mainboard/dell/dell_system_vostro_3360/gma-mainboard.ads
@@ -0,0 +1,34 @@
+--
+-- This file is part of the coreboot project.
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ -- FIXME: check this
+ ports : constant Port_List :=
+ (DP1,
+ DP2,
+ DP3,
+ HDMI1,
+ HDMI2,
+ HDMI3,
+ Analog,
+ Internal);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/dell/dell_system_vostro_3360/gpio.c b/src/mainboard/dell/dell_system_vostro_3360/gpio.c
new file mode 100755
index 0000000..d7db210
--- /dev/null
+++ b/src/mainboard/dell/dell_system_vostro_3360/gpio.c
@@ -0,0 +1,241 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio2 = GPIO_MODE_NATIVE,
+ .gpio3 = GPIO_MODE_GPIO,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_GPIO,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_GPIO,
+ .gpio10 = GPIO_MODE_GPIO,
+ .gpio11 = GPIO_MODE_GPIO,
+ .gpio12 = GPIO_MODE_GPIO,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_GPIO,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_GPIO,
+ .gpio19 = GPIO_MODE_GPIO,
+ .gpio20 = GPIO_MODE_GPIO,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_GPIO,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_GPIO,
+ .gpio26 = GPIO_MODE_NATIVE,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_NATIVE,
+ .gpio31 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_OUTPUT,
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio5 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_INPUT,
+ .gpio9 = GPIO_DIR_INPUT,
+ .gpio10 = GPIO_DIR_INPUT,
+ .gpio11 = GPIO_DIR_INPUT,
+ .gpio12 = GPIO_DIR_INPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_INPUT,
+ .gpio16 = GPIO_DIR_INPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio18 = GPIO_DIR_INPUT,
+ .gpio19 = GPIO_DIR_INPUT,
+ .gpio20 = GPIO_DIR_INPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio22 = GPIO_DIR_OUTPUT,
+ .gpio23 = GPIO_DIR_OUTPUT,
+ .gpio24 = GPIO_DIR_OUTPUT,
+ .gpio25 = GPIO_DIR_INPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+ .gpio29 = GPIO_DIR_INPUT,
+ .gpio31 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio0 = GPIO_LEVEL_LOW,
+ .gpio22 = GPIO_LEVEL_HIGH,
+ .gpio23 = GPIO_LEVEL_LOW,
+ .gpio24 = GPIO_LEVEL_LOW,
+ .gpio28 = GPIO_LEVEL_LOW,
+ .gpio31 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+ .gpio24 = GPIO_RESET_RSMRST,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio1 = GPIO_INVERT,
+ .gpio3 = GPIO_INVERT,
+ .gpio7 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_NATIVE,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_GPIO,
+ .gpio41 = GPIO_MODE_GPIO,
+ .gpio42 = GPIO_MODE_GPIO,
+ .gpio43 = GPIO_MODE_GPIO,
+ .gpio44 = GPIO_MODE_NATIVE,
+ .gpio45 = GPIO_MODE_GPIO,
+ .gpio46 = GPIO_MODE_GPIO,
+ .gpio47 = GPIO_MODE_GPIO,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_GPIO,
+ .gpio51 = GPIO_MODE_GPIO,
+ .gpio52 = GPIO_MODE_GPIO,
+ .gpio53 = GPIO_MODE_GPIO,
+ .gpio54 = GPIO_MODE_GPIO,
+ .gpio55 = GPIO_MODE_GPIO,
+ .gpio56 = GPIO_MODE_GPIO,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_GPIO,
+ .gpio60 = GPIO_MODE_GPIO,
+ .gpio61 = GPIO_MODE_GPIO,
+ .gpio62 = GPIO_MODE_GPIO,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio33 = GPIO_DIR_OUTPUT,
+ .gpio34 = GPIO_DIR_OUTPUT,
+ .gpio35 = GPIO_DIR_INPUT,
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio37 = GPIO_DIR_OUTPUT,
+ .gpio38 = GPIO_DIR_OUTPUT,
+ .gpio39 = GPIO_DIR_OUTPUT,
+ .gpio40 = GPIO_DIR_INPUT,
+ .gpio41 = GPIO_DIR_INPUT,
+ .gpio42 = GPIO_DIR_INPUT,
+ .gpio43 = GPIO_DIR_INPUT,
+ .gpio45 = GPIO_DIR_INPUT,
+ .gpio46 = GPIO_DIR_INPUT,
+ .gpio47 = GPIO_DIR_INPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_OUTPUT,
+ .gpio50 = GPIO_DIR_INPUT,
+ .gpio51 = GPIO_DIR_INPUT,
+ .gpio52 = GPIO_DIR_OUTPUT,
+ .gpio53 = GPIO_DIR_INPUT,
+ .gpio54 = GPIO_DIR_INPUT,
+ .gpio55 = GPIO_DIR_INPUT,
+ .gpio56 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+ .gpio59 = GPIO_DIR_INPUT,
+ .gpio60 = GPIO_DIR_OUTPUT,
+ .gpio61 = GPIO_DIR_INPUT,
+ .gpio62 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio33 = GPIO_LEVEL_HIGH,
+ .gpio34 = GPIO_LEVEL_HIGH,
+ .gpio37 = GPIO_LEVEL_LOW,
+ .gpio38 = GPIO_LEVEL_HIGH,
+ .gpio39 = GPIO_LEVEL_HIGH,
+ .gpio49 = GPIO_LEVEL_HIGH,
+ .gpio52 = GPIO_LEVEL_LOW,
+ .gpio60 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_GPIO,
+ .gpio65 = GPIO_MODE_NATIVE,
+ .gpio66 = GPIO_MODE_NATIVE,
+ .gpio67 = GPIO_MODE_NATIVE,
+ .gpio68 = GPIO_MODE_GPIO,
+ .gpio69 = GPIO_MODE_GPIO,
+ .gpio70 = GPIO_MODE_GPIO,
+ .gpio71 = GPIO_MODE_GPIO,
+ .gpio72 = GPIO_MODE_GPIO,
+ .gpio73 = GPIO_MODE_NATIVE,
+ .gpio74 = GPIO_MODE_GPIO,
+ .gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio64 = GPIO_DIR_INPUT,
+ .gpio68 = GPIO_DIR_INPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+ .gpio70 = GPIO_DIR_INPUT,
+ .gpio71 = GPIO_DIR_INPUT,
+ .gpio72 = GPIO_DIR_INPUT,
+ .gpio74 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/dell/dell_system_vostro_3360/hda_verb.c b/src/mainboard/dell/dell_system_vostro_3360/hda_verb.c
new file mode 100755
index 0000000..c55bf3c
--- /dev/null
+++ b/src/mainboard/dell/dell_system_vostro_3360/hda_verb.c
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x10134213, /* Codec Vendor / Device ID: Cirrus */
+ 0x1028055c, /* Subsystem ID */
+ 6, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(0x0, 0x1028055c),
+ AZALIA_PIN_CFG(0x0, 0x04, 0x0421101f),
+ AZALIA_PIN_CFG(0x0, 0x05, 0x90170010),
+ AZALIA_PIN_CFG(0x0, 0x06, 0x04a1103e),
+ AZALIA_PIN_CFG(0x0, 0x07, 0x40f000f0),
+ AZALIA_PIN_CFG(0x0, 0x08, 0x90a60030),
+
+ 0x80862806, /* Codec Vendor / Device ID: Intel */
+ 0x80860101, /* Subsystem ID */
+ 4, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(0x3, 0x80860101),
+ AZALIA_PIN_CFG(0x3, 0x05, 0x18560010),
+ AZALIA_PIN_CFG(0x3, 0x06, 0x58560020),
+ AZALIA_PIN_CFG(0x3, 0x07, 0x58560030),
+
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/dell/dell_system_vostro_3360/mainboard.c b/src/mainboard/dell/dell_system_vostro_3360/mainboard.c
new file mode 100755
index 0000000..e5cfebf
--- /dev/null
+++ b/src/mainboard/dell/dell_system_vostro_3360/mainboard.c
@@ -0,0 +1,15 @@
+#include <device/device.h>
+#include <drivers/intel/gma/int15.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+static void mainboard_enable(struct device *dev)
+{
+ /* FIXME: fix these values. */
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
+ GMA_INT15_PANEL_FIT_DEFAULT,
+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/util/superiotool/ite.c b/util/superiotool/ite.c
index 81ab024..2f2cb57 100644
--- a/util/superiotool/ite.c
+++ b/util/superiotool/ite.c
@@ -274,6 +274,60 @@
{0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT},
{0x00,0x00,0x6a,0x00,0x6e,0x01,0x01,EOT}},
{EOT}}},
+ {0x8518, "IT8518", {
+ {NOLDN, "Chip ID",
+ {0x20,0x21, EOT},
+ {0x85,0x16, EOT}},
+ {NOLDN, "Chip Version",
+ {0x22,EOT},
+ {0x63,EOT}},
+ {NOLDN, "Super I/O Control Register (SIOCTRL)",
+ {0x23,EOT},
+ {0x01,EOT}},
+ {NOLDN, "Super I/O Configuration Register (SIOIRQ)",
+ {0x25,EOT},
+ {0x00,EOT}},
+ {NOLDN, "Super I/O General Purpose Register (SIOGP)",
+ {0x26,EOT},
+ {0x00,EOT}},
+ {NOLDN, "Super I/O Power Mode Register (SIOPWR)",
+ {0x2d,EOT},
+ {0x00,EOT}},
+ {0x01, "UART1",
+ {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT},
+ {0x00,0x03,0xf8,0x00,0x00,0x04,0x02,EOT}},
+ {0x02, "UART2",
+ {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT},
+ {0x00,0x02,0xf8,0x00,0x00,0x04,0x02,EOT}},
+ {0x04, "System Wakup-Up (SWUC)",
+ {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT},
+ {0x00,0x00,0x00,0x00,0x00,0x00,0x01,EOT}},
+ {0x05, "Mouse",
+ {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT},
+ {0x00,0x00,0x00,0x00,0x00,0x0C,0x01,EOT}},
+ {0x06, "Keyboard",
+ {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT},
+ {0x00,0x00,0x60,0x00,0x64,0x01,0x01,EOT}},
+ {0x0f, "Shared Memory/Flash Interface (SMFI)",
+ {0x30,0x60,0x61,0x62,0x63,0x70,0x71,
+ 0xf4,0xf5,EOT},
+ {0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ NANA,NANA,EOT}},
+ {0x10, "BRAM / Real Time Clock (RTC)",
+ {0x30,0x60,0x61,0x62,0x63,0x70,0x71,
+ 0xf1,0xf2,0xf3,0xf4,0xf5,EOT},
+ {0x00,0x00,0x70,0x00,0x72,0x08,0x01,
+ NANA,NANA,NANA,NANA,NANA,EOT}},
+ {0x11, "Power Management Interface Channel 1",
+ {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT},
+ {0x00,0x00,0x62,0x00,0x66,0x01,0x01,EOT}},
+ {0x12, "Power Management Interface Channel 2",
+ {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT},
+ {0x00,0x00,0x68,0x00,0x6c,0x01,0x01,EOT}},
+ {0x17, "Power Management Interface Channel 3",
+ {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT},
+ {0x00,0x00,0x6a,0x00,0x6e,0x01,0x01,EOT}},
+ {EOT}}},
{0x8528, "IT8528", {
{NOLDN, NULL,
{0x24,0x25,0x26,0x27,0x28,0x29,
@@ -1388,6 +1442,73 @@
{NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,
NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}},
{EOT}}},
+ {0x8518, "IT8518", {
+ {NOLDN, NULL,
+ {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,
+ 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,EOT},
+ {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,
+ NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}},
+ {NOLDN, NULL,
+ {0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,
+ 0x18,0x19,0x1a,0x1b,0x1c,0x1d,0x1e,0x1f,EOT},
+ {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,
+ NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}},
+ {NOLDN, NULL,
+ {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,
+ 0x28,0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT},
+ {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,
+ NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}},
+ {NOLDN, NULL,
+ {0x30,0x31,0x32,0x33,0x34,0x35,0x36,0x37,
+ 0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,EOT},
+ {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,
+ NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}},
+ {NOLDN, NULL,
+ {0x40,0x41,0x42,0x43,0x44,0x45,0x46,0x47,
+ 0x48,0x49,0x4a,0x4b,0x4c,0x4d,0x4e,0x4f,EOT},
+ {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,
+ NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}},
+ {NOLDN, NULL,
+ {0x50,0x51,0x52,0x53,0x54,0x55,0x56,0x57,
+ 0x58,0x59,0x5a,0x5b,0x5c,0x5d,0x5e,0x5f,EOT},
+ {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,
+ NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}},
+ {NOLDN, NULL,
+ {0x60,0x61,0x62,0x63,0x64,0x65,0x66,0x67,
+ 0x68,0x69,0x6a,0x6b,0x6c,0x6d,0x6e,0x6f,EOT},
+ {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,
+ NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}},
+ {NOLDN, NULL,
+ {0x70,0x71,0x72,0x73,0x74,0x75,0x76,0x77,
+ 0x78,0x79,0x7a,0x7b,0x7c,0x7d,0x7e,0x7f,EOT},
+ {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,
+ NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}},
+ {NOLDN, NULL,
+ {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,
+ 0x88,0x89,0x8a,0x8b,0x8c,0x8d,0x8e,0x8f,EOT},
+ {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,
+ NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}},
+ {NOLDN, NULL,
+ {0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,
+ 0x98,0x99,0x9a,0x9b,0x9c,0x9d,0x9e,0x9f,EOT},
+ {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,
+ NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}},
+ {NOLDN, NULL,
+ {0xa0,0xa1,0xa2,0xa3,0xa4,0xa5,0xa6,0xa7,
+ 0xa8,0xa9,0xaa,0xab,0xac,0xad,0xae,0xaf,EOT},
+ {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,
+ NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}},
+ {NOLDN, NULL,
+ {0xb0,0xb1,0xb2,0xb3,0xb4,0xb5,0xb6,0xb7,
+ 0xb8,0xb9,0xba,0xbb,0xbc,0xbd,0xbe,0xbf,EOT},
+ {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,
+ NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}},
+ {NOLDN, NULL,
+ {0xc0,0xc1,0xc2,0xc3,0xc4,0xc5,0xc6,0xc7,
+ 0xc8,0xc9,0xca,0xcb,0xcc,0xcd,0xce,0xcf,EOT},
+ {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,
+ NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}},
+ {EOT}}},
{0x8987, "IT8987", {
{NOLDN, NULL,
{0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,
diff --git a/util/superiotool/output b/util/superiotool/output
new file mode 100644
index 0000000..fdf8a94
--- /dev/null
+++ b/util/superiotool/output
@@ -0,0 +1,500 @@
+superiotool r4.11-1185-g6824173704
+Found Aspeed AST2400 (id=0x00) at 0x4e
+Register dump:
+idx val def
+0x20: 0x85 (0x00)
+0x21: 0x18 (0x00)
+0x22: 0x08 (0x00)
+0x23: 0x01 (0x00)
+0x24: 0x00 (0x00)
+0x25: 0x00 (0x00)
+0x26: 0x00 (0x00)
+0x27: 0x00 (0x00)
+0x28: 0x00 (0x00)
+0x29: 0x00 (0x00)
+0x2a: 0x00 (0x00)
+0x2b: 0x00 (0x00)
+0x2c: 0x01 (0x00)
+0x2d: 0x00 (0x00)
+0x2e: 0x00 (0x00)
+0x2f: 0x00 (0x00)
+
+LDN 0x02 (SUART1)
+idx val def
+0x30: 0x00 (0x00)
+0x60: 0x02 (0x03)
+0x61: 0xf8 (0xf8)
+0x70: 0x03 (0x04)
+0x71: 0x02 (0x02)
+0xf0: 0x00 (RR)
+
+LDN 0x03 (SUART2)
+idx val def
+0x30: 0x00 (0x00)
+0x60: 0x00 (0x02)
+0x61: 0x00 (0xf8)
+0x70: 0x00 (0x03)
+0x71: 0x00 (0x02)
+0xf0: 0x00 (0x00)
+
+LDN 0x04 (SWC)
+idx val def
+0x30: 0x00 (0x00)
+0x60: 0x00 (0x08)
+0x61: 0x00 (0xe6)
+0x62: 0x00 (0x08)
+0x63: 0x00 (0xe0)
+0x64: 0x00 (0x08)
+0x65: 0x00 (0xe4)
+0x66: 0x00 (0x08)
+0x67: 0x00 (0xe8)
+0x70: 0x00 (0x09)
+0x71: 0x01 (0x01)
+
+LDN 0x05 (Keyboard config (KBC))
+idx val def
+0x30: 0x01 (0x00)
+0x60: 0x00 (0x00)
+0x61: 0x00 (0x60)
+0x62: 0x00 (0x00)
+0x63: 0x00 (0x64)
+0x70: 0x0c (0x01)
+0x71: 0x01 (0x02)
+0x72: 0x00 (0x0c)
+0x73: 0x00 (0x02)
+0xf0: 0x00 (0x83)
+
+LDN 0x07 (GPIO)
+idx val def
+0x30: 0x00 (0x00)
+0x38: 0x00 (0x00)
+0x70: 0x00 (0x0b)
+0x71: 0x00 (0x01)
+
+LDN 0x0b (SUART3)
+idx val def
+0x30: 0x00 (0x00)
+0x60: 0x00 (0x03)
+0x61: 0x00 (0xe8)
+0x70: 0x00 (0x06)
+0x71: 0x00 (0x02)
+0xf0: 0x00 (0x00)
+
+LDN 0x0c (SUART4)
+idx val def
+0x30: 0x00 (0x00)
+0x60: 0x00 (0x02)
+0x61: 0x00 (0xe8)
+0x70: 0x00 (0x05)
+0x71: 0x00 (0x02)
+0xf0: 0x00 (0x00)
+
+LDN 0x0d (iLPC2AHB)
+idx val def
+0x30: 0x00 (0x00)
+0x70: 0x00 (0x09)
+0x71: 0x00 (0x01)
+0xf0: 0x00 (NA)
+0xf1: 0x00 (NA)
+0xf2: 0x00 (NA)
+0xf3: 0x00 (NA)
+0xf4: 0x00 (NA)
+0xf5: 0x00 (NA)
+0xf6: 0x00 (NA)
+0xf7: 0x00 (NA)
+0xf8: 0x00 (0x00)
+0xfe: 0x00 (0x00)
+
+LDN 0x0e (Mailbox)
+idx val def
+0x30: 0x00 (0x00)
+0x60: 0x00 (0x08)
+0x61: 0x00 (0xc0)
+0x70: 0x00 (0x09)
+0x71: 0x00 (0x01)
+
+Found ITE IT8516??? (id=0x8518, rev=0x8) at 0x4e
+(Chip ID)
+idx val def
+0x20: 0x85 (0x85)
+0x21: 0x18 (0x16)
+
+(Chip Version)
+idx val def
+0x22: 0x08 (0x63)
+
+(Super I/O Control Register (SIOCTRL))
+idx val def
+0x23: 0x01 (0x01)
+
+(Super I/O Configuration Register (SIOIRQ))
+idx val def
+0x25: 0x00 (0x00)
+
+(Super I/O General Purpose Register (SIOGP))
+idx val def
+0x26: 0x00 (0x00)
+
+(Super I/O Power Mode Register (SIOPWR))
+idx val def
+0x2d: 0x00 (0x00)
+
+LDN 0x01 (UART1)
+idx val def
+0x30: 0x00 (0x00)
+0x60: 0x03 (0x03)
+0x61: 0xf8 (0xf8)
+0x62: 0x00 (0x00)
+0x63: 0x00 (0x00)
+0x70: 0x04 (0x04)
+0x71: 0x02 (0x02)
+
+LDN 0x02 (UART2)
+idx val def
+0x30: 0x00 (0x00)
+0x60: 0x02 (0x02)
+0x61: 0xf8 (0xf8)
+0x62: 0x00 (0x00)
+0x63: 0x00 (0x00)
+0x70: 0x03 (0x04)
+0x71: 0x02 (0x02)
+
+LDN 0x04 (System Wakup-Up (SWUC))
+idx val def
+0x30: 0x00 (0x00)
+0x60: 0x00 (0x00)
+0x61: 0x00 (0x00)
+0x62: 0x00 (0x00)
+0x63: 0x00 (0x00)
+0x70: 0x00 (0x00)
+0x71: 0x01 (0x01)
+
+LDN 0x05 (Mouse)
+idx val def
+0x30: 0x01 (0x00)
+0x60: 0x00 (0x00)
+0x61: 0x00 (0x00)
+0x62: 0x00 (0x00)
+0x63: 0x00 (0x00)
+0x70: 0x0c (0x0c)
+0x71: 0x01 (0x01)
+
+LDN 0x06 (Keyboard)
+idx val def
+0x30: 0x01 (0x00)
+0x60: 0x00 (0x00)
+0x61: 0x60 (0x60)
+0x62: 0x00 (0x00)
+0x63: 0x64 (0x64)
+0x70: 0x01 (0x01)
+0x71: 0x01 (0x01)
+
+LDN 0x0f (Shared Memory/Flash Interface (SMFI))
+idx val def
+0x30: 0x00 (0x00)
+0x60: 0x00 (0x00)
+0x61: 0x00 (0x00)
+0x62: 0x00 (0x00)
+0x63: 0x00 (0x00)
+0x70: 0x00 (0x00)
+0x71: 0x00 (0x00)
+0xf4: 0x00 (NA)
+0xf5: 0x00 (NA)
+
+LDN 0x10 (BRAM / Real Time Clock (RTC))
+idx val def
+0x30: 0x01 (0x00)
+0x60: 0x00 (0x00)
+0x61: 0x70 (0x70)
+0x62: 0x09 (0x00)
+0x63: 0x10 (0x72)
+0x70: 0x08 (0x08)
+0x71: 0x01 (0x01)
+0xf1: 0x00 (NA)
+0xf2: 0x00 (NA)
+0xf3: 0x00 (NA)
+0xf4: 0x3f (NA)
+0xf5: 0x3f (NA)
+
+LDN 0x11 (Power Management Interface Channel 1)
+idx val def
+0x30: 0x01 (0x00)
+0x60: 0x00 (0x00)
+0x61: 0x62 (0x62)
+0x62: 0x00 (0x00)
+0x63: 0x66 (0x66)
+0x70: 0x00 (0x01)
+0x71: 0x01 (0x01)
+
+LDN 0x12 (Power Management Interface Channel 2)
+idx val def
+0x30: 0x01 (0x00)
+0x60: 0x00 (0x00)
+0x61: 0x68 (0x68)
+0x62: 0x00 (0x00)
+0x63: 0x6c (0x6c)
+0x70: 0x00 (0x01)
+0x71: 0x01 (0x01)
+
+LDN 0x17 (Power Management Interface Channel 3)
+idx val def
+0x30: 0x01 (0x00)
+0x60: 0x06 (0x00)
+0x61: 0xa0 (0x6a)
+0x62: 0x06 (0x00)
+0x63: 0xa4 (0x6e)
+0x70: 0x01 (0x01)
+0x71: 0x01 (0x01)
+
+Environment controller (0x0005)
+BRAM (0x0910)
+Register dump:
+idx val def
+0x00: 0x12 (NA)
+0x01: 0x03 (NA)
+0x02: 0x00 (NA)
+0x03: 0x00 (NA)
+0x04: 0x01 (NA)
+0x05: 0x00 (NA)
+0x06: 0x02 (NA)
+0x07: 0x00 (NA)
+0x08: 0xa3 (NA)
+0x09: 0xff (NA)
+0x0a: 0xff (NA)
+0x0b: 0x00 (NA)
+0x0c: 0x00 (NA)
+0x0d: 0x00 (NA)
+0x0e: 0x00 (NA)
+0x0f: 0x00 (NA)
+
+Register dump:
+idx val def
+0x10: 0x00 (NA)
+0x11: 0x00 (NA)
+0x12: 0x00 (NA)
+0x13: 0x00 (NA)
+0x14: 0x00 (NA)
+0x15: 0x00 (NA)
+0x16: 0x00 (NA)
+0x17: 0x00 (NA)
+0x18: 0x00 (NA)
+0x19: 0x00 (NA)
+0x1a: 0x00 (NA)
+0x1b: 0x00 (NA)
+0x1c: 0x00 (NA)
+0x1d: 0x00 (NA)
+0x1e: 0x02 (NA)
+0x1f: 0x00 (NA)
+
+Register dump:
+idx val def
+0x20: 0x01 (NA)
+0x21: 0x10 (NA)
+0x22: 0x00 (NA)
+0x23: 0x00 (NA)
+0x24: 0x00 (NA)
+0x25: 0x00 (NA)
+0x26: 0x00 (NA)
+0x27: 0x00 (NA)
+0x28: 0x00 (NA)
+0x29: 0x00 (NA)
+0x2a: 0x00 (NA)
+0x2b: 0x00 (NA)
+0x2c: 0x00 (NA)
+0x2d: 0x00 (NA)
+0x2e: 0x00 (NA)
+0x2f: 0x00 (NA)
+
+Register dump:
+idx val def
+0x30: 0x00 (NA)
+0x31: 0x00 (NA)
+0x32: 0x24 (NA)
+0x33: 0x00 (NA)
+0x34: 0x00 (NA)
+0x35: 0x10 (NA)
+0x36: 0x00 (NA)
+0x37: 0x00 (NA)
+0x38: 0x00 (NA)
+0x39: 0x00 (NA)
+0x3a: 0x88 (NA)
+0x3b: 0x27 (NA)
+0x3c: 0x68 (NA)
+0x3d: 0x00 (NA)
+0x3e: 0x00 (NA)
+0x3f: 0x00 (NA)
+
+Register dump:
+idx val def
+0x40: 0x00 (NA)
+0x41: 0x00 (NA)
+0x42: 0x00 (NA)
+0x43: 0x00 (NA)
+0x44: 0x00 (NA)
+0x45: 0x00 (NA)
+0x46: 0x00 (NA)
+0x47: 0x00 (NA)
+0x48: 0x00 (NA)
+0x49: 0x00 (NA)
+0x4a: 0x00 (NA)
+0x4b: 0x00 (NA)
+0x4c: 0x00 (NA)
+0x4d: 0x00 (NA)
+0x4e: 0x00 (NA)
+0x4f: 0x00 (NA)
+
+Register dump:
+idx val def
+0x50: 0x00 (NA)
+0x51: 0x00 (NA)
+0x52: 0x00 (NA)
+0x53: 0x00 (NA)
+0x54: 0x00 (NA)
+0x55: 0x00 (NA)
+0x56: 0x00 (NA)
+0x57: 0x00 (NA)
+0x58: 0x00 (NA)
+0x59: 0x00 (NA)
+0x5a: 0x00 (NA)
+0x5b: 0x00 (NA)
+0x5c: 0x00 (NA)
+0x5d: 0x00 (NA)
+0x5e: 0x00 (NA)
+0x5f: 0x00 (NA)
+
+Register dump:
+idx val def
+0x60: 0x00 (NA)
+0x61: 0x00 (NA)
+0x62: 0x00 (NA)
+0x63: 0x00 (NA)
+0x64: 0x00 (NA)
+0x65: 0x00 (NA)
+0x66: 0x00 (NA)
+0x67: 0x00 (NA)
+0x68: 0x00 (NA)
+0x69: 0x00 (NA)
+0x6a: 0x00 (NA)
+0x6b: 0x00 (NA)
+0x6c: 0x00 (NA)
+0x6d: 0x00 (NA)
+0x6e: 0x00 (NA)
+0x6f: 0x00 (NA)
+
+Register dump:
+idx val def
+0x70: 0x00 (NA)
+0x71: 0x00 (NA)
+0x72: 0x00 (NA)
+0x73: 0x00 (NA)
+0x74: 0x00 (NA)
+0x75: 0x00 (NA)
+0x76: 0x00 (NA)
+0x77: 0x00 (NA)
+0x78: 0x00 (NA)
+0x79: 0x00 (NA)
+0x7a: 0x00 (NA)
+0x7b: 0x00 (NA)
+0x7c: 0x00 (NA)
+0x7d: 0x00 (NA)
+0x7e: 0x00 (NA)
+0x7f: 0x00 (NA)
+
+Register dump:
+idx val def
+0x80: 0x12 (NA)
+0x81: 0x03 (NA)
+0x82: 0x00 (NA)
+0x83: 0x00 (NA)
+0x84: 0x01 (NA)
+0x85: 0x00 (NA)
+0x86: 0x02 (NA)
+0x87: 0x00 (NA)
+0x88: 0xa3 (NA)
+0x89: 0xff (NA)
+0x8a: 0xff (NA)
+0x8b: 0x00 (NA)
+0x8c: 0x00 (NA)
+0x8d: 0x00 (NA)
+0x8e: 0x00 (NA)
+0x8f: 0x00 (NA)
+
+Register dump:
+idx val def
+0x90: 0x00 (NA)
+0x91: 0x00 (NA)
+0x92: 0x00 (NA)
+0x93: 0x00 (NA)
+0x94: 0x00 (NA)
+0x95: 0x00 (NA)
+0x96: 0x00 (NA)
+0x97: 0x00 (NA)
+0x98: 0x00 (NA)
+0x99: 0x00 (NA)
+0x9a: 0x00 (NA)
+0x9b: 0x00 (NA)
+0x9c: 0x00 (NA)
+0x9d: 0x00 (NA)
+0x9e: 0x02 (NA)
+0x9f: 0x00 (NA)
+
+Register dump:
+idx val def
+0xa0: 0x01 (NA)
+0xa1: 0x10 (NA)
+0xa2: 0x00 (NA)
+0xa3: 0x00 (NA)
+0xa4: 0x00 (NA)
+0xa5: 0x00 (NA)
+0xa6: 0x00 (NA)
+0xa7: 0x00 (NA)
+0xa8: 0x00 (NA)
+0xa9: 0x00 (NA)
+0xaa: 0x00 (NA)
+0xab: 0x00 (NA)
+0xac: 0x00 (NA)
+0xad: 0x00 (NA)
+0xae: 0x00 (NA)
+0xaf: 0x00 (NA)
+
+Register dump:
+idx val def
+0xb0: 0x00 (NA)
+0xb1: 0x00 (NA)
+0xb2: 0x24 (NA)
+0xb3: 0x00 (NA)
+0xb4: 0x00 (NA)
+0xb5: 0x10 (NA)
+0xb6: 0x00 (NA)
+0xb7: 0x00 (NA)
+0xb8: 0x00 (NA)
+0xb9: 0x00 (NA)
+0xba: 0x88 (NA)
+0xbb: 0x27 (NA)
+0xbc: 0x68 (NA)
+0xbd: 0x00 (NA)
+0xbe: 0x00 (NA)
+0xbf: 0x00 (NA)
+
+Register dump:
+idx val def
+0xc0: 0x00 (NA)
+0xc1: 0x00 (NA)
+0xc2: 0x00 (NA)
+0xc3: 0x00 (NA)
+0xc4: 0x00 (NA)
+0xc5: 0x00 (NA)
+0xc6: 0x00 (NA)
+0xc7: 0x00 (NA)
+0xc8: 0x00 (NA)
+0xc9: 0x00 (NA)
+0xca: 0x00 (NA)
+0xcb: 0x00 (NA)
+0xcc: 0x00 (NA)
+0xcd: 0x00 (NA)
+0xce: 0x00 (NA)
+0xcf: 0x00 (NA)
+
+Found SMSC SCH5317 (id=0x85, rev=0x18) at 0x4e
+No dump available for this Super I/O
+No extra registers known for this chip.
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