Tim Wawrzynczak has uploaded this change for review.
soc/intel/jasperlake: Add JSL PMC as 'hidden' PCI device
This change allows treating the PMC as a 'hidden' PCI device on Jasper
Lake, so that the MMIO & I/O resources can be exposed as belonging to
this device, instead of the system agent and LPC/eSPI.
Change-Id: Ie07987c68388d03359c43f64a849dc6e3f94676e
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
---
M src/mainboard/google/dedede/variants/baseboard/devicetree.cb
M src/soc/intel/jasperlake/chip.c
M src/soc/intel/jasperlake/espi.c
M src/soc/intel/jasperlake/pmc.c
M src/soc/intel/jasperlake/systemagent.c
5 files changed, 24 insertions(+), 38 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/42018/1
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
index a856b22..b511259 100644
--- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
@@ -300,7 +300,7 @@
end
end # eSPI Interface
device pci 1f.1 on end # P2SB
- device pci 1f.2 on end # Power Management Controller
+ device pci 1f.2 hidden end # Power Management Controller
device pci 1f.3 off end # Intel HDA/cAVS
device pci 1f.4 off end # SMBus
device pci 1f.5 on end # PCH SPI
diff --git a/src/soc/intel/jasperlake/chip.c b/src/soc/intel/jasperlake/chip.c
index 6f4ee00..ff63398 100644
--- a/src/soc/intel/jasperlake/chip.c
+++ b/src/soc/intel/jasperlake/chip.c
@@ -150,6 +150,7 @@
#endif
};
+extern struct device_operations pmc_ops;
static void soc_enable(struct device *dev)
{
/* Set the operations if it is a special bus type */
@@ -157,6 +158,9 @@
dev->ops = &pci_domain_ops;
else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)
dev->ops = &cpu_bus_ops;
+ else if (dev->path.type == DEVICE_PATH_PCI &&
+ dev->path.pci.devfn == PCH_DEVFN_PMC)
+ dev->ops = &pmc_ops;
}
struct chip_operations soc_intel_jasperlake_ops = {
diff --git a/src/soc/intel/jasperlake/espi.c b/src/soc/intel/jasperlake/espi.c
index 7acd0a0..a1954fd 100644
--- a/src/soc/intel/jasperlake/espi.c
+++ b/src/soc/intel/jasperlake/espi.c
@@ -191,21 +191,4 @@
soc_mirror_dmi_pcr_io_dec();
}
-/* Fill up ESPI IO resource structure inside SoC directory */
-void pch_lpc_soc_fill_io_resources(struct device *dev)
-{
- /*
- * PMC pci device gets hidden from PCI bus due to Silicon
- * policy hence bind ACPI BASE aka ABASE (offset 0x20) with
- * ESPI IO resources to ensure that ABASE falls under PCI reserved
- * IO memory range.
- *
- * Note: Don't add any more resource with same offset 0x20
- * under this device space.
- */
- pch_lpc_add_new_resource(dev, PCI_BASE_ADDRESS_4,
- ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, IORESOURCE_IO |
- IORESOURCE_ASSIGNED | IORESOURCE_FIXED);
-}
-
#endif
diff --git a/src/soc/intel/jasperlake/pmc.c b/src/soc/intel/jasperlake/pmc.c
index 5bd4438..4443055 100644
--- a/src/soc/intel/jasperlake/pmc.c
+++ b/src/soc/intel/jasperlake/pmc.c
@@ -69,7 +69,7 @@
write32(pmcbase + DSX_CFG, reg);
}
-static void pmc_init(void *unused)
+static void pmc_init(struct device *dev)
{
const config_t *config = config_of_soc();
@@ -85,11 +85,21 @@
config_deep_sx(config->deep_sx_config);
}
-/*
-* Initialize PMC controller.
-*
-* PMC controller gets hidden from PCI bus during FSP-Silicon init call.
-* Hence PCI enumeration can't be used to initialize bus device and
-* allocate resources.
-*/
-BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_EXIT, pmc_init, NULL);
+static void soc_pmc_read_resources(struct device *dev)
+{
+ struct resource *res;
+
+ mmio_resource(dev, 0, PCH_PWRM_BASE_ADDRESS / KiB, PCH_PWRM_BASE_SIZE / KiB);
+
+ res = new_resource(dev, 1);
+ res->base = (resource_t)ACPI_BASE_ADDRESS;
+ res->size = (resource_t)ACPI_BASE_SIZE;
+ res->limit = res->base + res->size + 1;
+ res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+}
+
+struct device_operations pmc_ops = {
+ .read_resources = soc_pmc_read_resources,
+ .set_resources = noop_set_resources,
+ .enable = pmc_init,
+};
diff --git a/src/soc/intel/jasperlake/systemagent.c b/src/soc/intel/jasperlake/systemagent.c
index db56cc0..072db79 100644
--- a/src/soc/intel/jasperlake/systemagent.c
+++ b/src/soc/intel/jasperlake/systemagent.c
@@ -23,17 +23,6 @@
{ EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" },
{ REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" },
{ EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" },
- /*
- * PMC pci device gets hidden from PCI bus due to Silicon
- * policy hence binding PMCBAR aka PWRMBASE (offset 0x10) with
- * SA resources to ensure that PMCBAR falls under PCI reserved
- * memory range.
- *
- * Note: Don't add any more resource with same offset 0x10
- * under this device space.
- */
- { PCI_BASE_ADDRESS_0, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE,
- "PMCBAR" },
};
sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources,
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