Marshall Dawson uploaded patch set #12 to the change originally created by Kyösti Mälkki.
arch/x86: Implement RESET_VECTOR_IN_RAM for bootblock
Add support for devices with the reset vector pointing into DRAM. This
is a specific implementation that assumes a paradigm of AMD Family 17h
(a.k.a. "Zen"). Until the first ljmpl for protected mode, the core's
state appears to software like other designs, and then the actual
physical addressing becomes recognizable.
Due the nature of a system where the DRAM is alive before the x86, a
number of design options were considered, including the first stage as
ramstage. Beginning with ramstage was infeasible because the processor
must still go through the typical initial steps and be put into flat
protected mode.
This patch is phase 1 of adding support and it builds a traditional
bootblock image. Although running from DRAM, the unused bootblock
is kept in cbfs. The details for placing the bootblock into memory
are left to the soc implementation.
Sample build using amd/mandolin (currently WIP):
Name Offset Type Size Comp
cbfs master header 0x0 cbfs header 32 none
fallback/romstage 0x80 stage 21188 none
fallback/ramstage 0x53c0 stage 76271 none
config 0x17e00 raw 334 none
revision 0x17fc0 raw 674 none
payload_config 0x182c0 raw 1621 none
payload_revision 0x18980 raw 264 none
(empty) 0x18b00 null 664 none
fspm.bin 0x18dc0 fsp 720896 none
(empty) 0xc8e00 null 3992 none
fsps.bin 0xc9dc0 fsp 327680 none
pci1002,15d8.rom 0x119e00 optionrom 54272 none
fallback/dsdt.aml 0x127280 raw 8372 none
fallback/payload 0x129380 simple elf 69496 none
(empty) 0x13a340 null 2382424 none
bootblock 0x37fdc0 bootblock 524288 none
readelf of build/cbfs/fallback/bootblock.elf:
Section Headers:
[Nr] Name Type Addr Off Size ES Flg Lk Inf Al
[ 0] NULL 00000000 000000 000000 00 0 0 0
[ 1] .text PROGBITS 08000000 001000 0049c0 00 AX 0 0 32
[ 2] .rel.text REL 00000000 082f00 001240 08 I 9 1 4
[ 3] .earlyram.data NOBITS 0802cf4a 0059c0 002106 00 WA 0 0 4
[ 4] .near_reset_vecto PROGBITS 0807f000 080000 0000bf 00 AX 0 0 4096
[ 5] .rel.near_reset_v REL 00000000 084140 000040 08 I 9 4 4
[ 6] .reset PROGBITS 0807fff0 080ff0 000010 00 AX 0 0 1
[ 7] .rel.reset REL 00000000 084180 000008 08 I 9 6 4
[ 8] .gnu_debuglink PROGBITS 00000000 081000 000014 00 0 0 4
[ 9] .symtab SYMTAB 00000000 081014 0010a0 10 10 96 4
[10] .strtab STRTAB 00000000 0820b4 000e49 00 0 0 1
[11] .shstrtab STRTAB 00000000 084188 000065 00 0 0 1
137: 0802cf50 0 NOTYPE GLOBAL DEFAULT 3 _earlyram_stack
107: 0802d750 0 NOTYPE GLOBAL DEFAULT 3 _eearlyram_stack
216: 0802d750 0 NOTYPE GLOBAL DEFAULT 3 _preram_cbmem_console
240: 0802ed50 0 NOTYPE GLOBAL DEFAULT 3 _epreram_cbmem_console
162: 0802ed50 0 NOTYPE GLOBAL DEFAULT 3 _timestamp
258: 0802ef50 0 NOTYPE GLOBAL DEFAULT 3 _etimestamp
128: 0802ef50 0 NOTYPE GLOBAL DEFAULT 3 _fmap_cache
159: 0802f006 0 NOTYPE GLOBAL DEFAULT 3 _efmap_cache
190: 0802f008 0 NOTYPE GLOBAL DEFAULT 3 _bss
174: 0802f050 0 NOTYPE GLOBAL DEFAULT 3 _ebss
Change-Id: I9c084ff6fdcf7e9154436f038705e8679daea780
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
---
M Makefile.inc
M src/arch/x86/Kconfig
M src/arch/x86/assembly_entry.S
A src/arch/x86/early_ram.ld
M src/arch/x86/memlayout.ld
M src/cpu/Kconfig
M src/include/memlayout.h
7 files changed, 92 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/35035/12
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