Nico Huber uploaded patch set #2 to this change.

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nb/intel/ironlake: Reserve gap betwen TSEG and BGSM

There may be a gap between TSEG and the graphics stolen memory due to
the alignment done in `raminit.c`. If we allocate MMIO resources in
this range, it misbehaves unpredictably, so reserve it.

TEST=Booted Thinkpad X201s, allocated resources are above TOLUD.

Change-Id: If305e9751ebf4edc945cf038ed72698f3696e52d
Signed-off-by: Nico Huber <nico.h@gmx.de>
---
M src/northbridge/intel/ironlake/northbridge.c
1 file changed, 7 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/45325/2

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: If305e9751ebf4edc945cf038ed72698f3696e52d
Gerrit-Change-Number: 45325
Gerrit-PatchSet: 2
Gerrit-Owner: Nico Huber <nico.h@gmx.de>
Gerrit-Reviewer: Angel Pons <th3fanbus@gmail.com>
Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>
Gerrit-MessageType: newpatchset