Edward O'Callaghan (eocallaghan@alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5439
-gerrit
commit 83f9aa2b1a83cf3ce8e84abbdf720a3574ca9ed1 Author: Edward O'Callaghan eocallaghan@alterapraxis.com Date: Mon Mar 31 21:53:32 2014 +1100
superio/serverengines/pilot: Avoid .c includes
Following the same reasoning as commit d3043313a91dff3bc2f879ffb3b4bf23a364d711 superio/fintek/f81865f: Avoid .c includes Clean up the early_serial #include directives in mainboard/romstage code.
Change-Id: Ia6ed36c8517a95b651fefdd855eec0ec91d73187 Signed-off-by: Edward O'Callaghan eocallaghan@alterapraxis.com --- src/mainboard/hp/dl145_g3/Kconfig | 1 + src/mainboard/hp/dl145_g3/romstage.c | 3 +-- src/mainboard/hp/dl165_g6_fam10/Kconfig | 1 + src/mainboard/hp/dl165_g6_fam10/romstage.c | 3 +-- src/superio/Makefile.inc | 2 +- src/superio/serverengines/Makefile.inc | 20 ++++++++++++++++++++ src/superio/serverengines/pilot/Makefile.inc | 22 ++++++++++++++++++++++ src/superio/serverengines/pilot/early_init.c | 7 ++++++- src/superio/serverengines/pilot/early_serial.c | 9 +++++---- src/superio/serverengines/pilot/pilot.h | 11 ++++++++++- 10 files changed, 68 insertions(+), 11 deletions(-)
diff --git a/src/mainboard/hp/dl145_g3/Kconfig b/src/mainboard/hp/dl145_g3/Kconfig index be3f009..3ff5f0b 100644 --- a/src/mainboard/hp/dl145_g3/Kconfig +++ b/src/mainboard/hp/dl145_g3/Kconfig @@ -9,6 +9,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_BROADCOM_BCM21000 select SOUTHBRIDGE_BROADCOM_BCM5785 + select SUPERIO_SERVERENGINES_PILOT select SUPERIO_NSC_PC87417 select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c index 0d8e9d2..9deaaba 100644 --- a/src/mainboard/hp/dl145_g3/romstage.c +++ b/src/mainboard/hp/dl145_g3/romstage.c @@ -40,8 +40,7 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/serverengines/pilot/early_serial.c" -#include "superio/serverengines/pilot/early_init.c" +#include <superio/serverengines/pilot/pilot.h> #include "superio/nsc/pc87417/early_serial.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" diff --git a/src/mainboard/hp/dl165_g6_fam10/Kconfig b/src/mainboard/hp/dl165_g6_fam10/Kconfig index b72b8dd..b53809a 100644 --- a/src/mainboard/hp/dl165_g6_fam10/Kconfig +++ b/src/mainboard/hp/dl165_g6_fam10/Kconfig @@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDFAM10 select SOUTHBRIDGE_BROADCOM_BCM21000 select SOUTHBRIDGE_BROADCOM_BCM5785 + select SUPERIO_SERVERENGINES_PILOT select SUPERIO_NSC_PC87417 select DIMM_DDR2 select DIMM_REGISTERED diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index 8e109c5..474190b 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -46,8 +46,7 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdfam10/reset_test.c" -#include "superio/serverengines/pilot/early_serial.c" -#include "superio/serverengines/pilot/early_init.c" +#include <superio/serverengines/pilot/pilot.h> #include "superio/nsc/pc87417/early_serial.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdfam10/debug.c" diff --git a/src/superio/Makefile.inc b/src/superio/Makefile.inc index e34fa89..2ca57cb 100644 --- a/src/superio/Makefile.inc +++ b/src/superio/Makefile.inc @@ -23,7 +23,7 @@ subdirs-y += ite subdirs-y += nsc subdirs-y += nuvoton subdirs-y += renesas -#subdirs-y += serverengines +subdirs-y += serverengines subdirs-y += smsc subdirs-y += via subdirs-y += winbond diff --git a/src/superio/serverengines/Makefile.inc b/src/superio/serverengines/Makefile.inc new file mode 100644 index 0000000..4ba0a24 --- /dev/null +++ b/src/superio/serverengines/Makefile.inc @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Edward O'Callaghan eocallaghan@alterapraxis.com +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +subdirs-y += pilot diff --git a/src/superio/serverengines/pilot/Makefile.inc b/src/superio/serverengines/pilot/Makefile.inc new file mode 100644 index 0000000..b07438f --- /dev/null +++ b/src/superio/serverengines/pilot/Makefile.inc @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Edward O'Callaghan eocallaghan@alterapraxis.com +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +romstage-$(CONFIG_SUPERIO_SERVERENGINES_PILOT) += early_init.c +romstage-$(CONFIG_SUPERIO_SERVERENGINES_PILOT) += early_serial.c diff --git a/src/superio/serverengines/pilot/early_init.c b/src/superio/serverengines/pilot/early_init.c index 1993c9e..002210f 100644 --- a/src/superio/serverengines/pilot/early_init.c +++ b/src/superio/serverengines/pilot/early_init.c @@ -23,11 +23,16 @@
#define BLUBB_DEV PNP_DEV(port, 0x04)
+#include <arch/io.h> +#include <console/console.h> +#include <device/pnp.h> +#include "pilot.h" + /* * Logical device 4, 5 and 7 are being deactivated. Logical Device 1 seems to * be another serial (?), it is also deactivated on the HP machine. */ -static void pilot_early_init(device_t dev) +void pilot_early_init(device_t dev) { u16 port = dev >> 8;
diff --git a/src/superio/serverengines/pilot/early_serial.c b/src/superio/serverengines/pilot/early_serial.c index 4112901..82e124c 100644 --- a/src/superio/serverengines/pilot/early_serial.c +++ b/src/superio/serverengines/pilot/early_serial.c @@ -22,23 +22,24 @@ /* PILOT Super I/O is only based on LPC observation done on factory system. */
#include <arch/io.h> +#include <device/pnp.h> #include "pilot.h"
/* Pilot uses 0x5A/0xA5 pattern to actiavte deactivate config access. */ -static void pnp_enter_ext_func_mode(device_t dev) +void pnp_enter_ext_func_mode(device_t dev) { u16 port = dev >> 8; outb(0x5A, port); }
-static void pnp_exit_ext_func_mode(device_t dev) +void pnp_exit_ext_func_mode(device_t dev) { u16 port = dev >> 8; outb(0xA5, port); }
/* Serial config is a fairly standard procedure. */ -static void __attribute__((unused)) pilot_enable_serial(device_t dev, u16 iobase) +void pilot_enable_serial(device_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); @@ -47,7 +48,7 @@ static void __attribute__((unused)) pilot_enable_serial(device_t dev, u16 iobase pnp_exit_ext_func_mode(dev); }
-static void __attribute__((unused)) pilot_disable_serial(device_t dev) +void pilot_disable_serial(device_t dev) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); diff --git a/src/superio/serverengines/pilot/pilot.h b/src/superio/serverengines/pilot/pilot.h index a5bddd3..e19cf37 100644 --- a/src/superio/serverengines/pilot/pilot.h +++ b/src/superio/serverengines/pilot/pilot.h @@ -30,4 +30,13 @@ #define PILOT_LD5 0x05 /* Logical device 5 */ #define PILOT_LD7 0x07 /* Logical device 7 */
-#endif +/* should not expose these however early_init needs love */ +void pnp_enter_ext_func_mode(device_t dev); +void pnp_exit_ext_func_mode(device_t dev); + +void pilot_early_init(device_t dev); + +void pilot_enable_serial(device_t dev, u16 iobase); +void pilot_disable_serial(device_t dev); + +#endif /* SUPERIO_SERVERENGINES_PILOT_PILOT_H */