Patrick Rudolph has uploaded this change for review.
nb/intel/sandybridge/raminit: Set REFIx9 according to spec
Set tREFIx9 to 8.9*tREFI/1024 as suggested in
xeon-e3-1200v3-vol-2-datasheet.pdf chapter 4.2.15 or
2nd-gen-core-family-mobile-vol-2-datasheet chapter 2.14.1.
Use the minimum value of REFI*8.9 and tRASmax as suggested by
3rd-gen-core-desktop-vol-2-datasheet.pdf chapter 2.13.9.
Change-Id: Ifd32a70f28aa75418030b0e4d1fc7d539a315f83
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
---
M src/northbridge/intel/sandybridge/raminit_common.c
1 file changed, 12 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/22259/1
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c
index eaef5f7..88357f6 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.c
+++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -263,16 +263,18 @@
dram_odt_stretch(ctrl, channel);
- // REFI
- reg = 0;
- val32 = ctrl->tREFI;
- reg = (reg & ~0xffff) | val32;
- val32 = ctrl->tRFC;
- reg = (reg & ~0x1ff0000) | (val32 << 16);
- val32 = (u32) (ctrl->tREFI * 9) / 1024;
- reg = (reg & ~0xfe000000) | (val32 << 25);
- printram("REFI [%x] = %x\n", 0x400 * channel + 0x4298,
- reg);
+ /*
+ * TC—Refresh timing parameters
+ * The tREFIx9 field should be programmed to minimum of
+ * 8.9*tREFI (to allow for possible delays from ZQ or
+ * isoc) and tRASmax (70us) divided by 1024.
+ */
+ val32 = MIN((ctrl->tREFI * 89) / 10, (70000 << 8) / ctrl->tCK);
+
+ reg = ((ctrl->tREFI & 0xffff) << 0) |
+ ((ctrl->tRFC & 0x1ff) << 16) |
+ (((val32 / 1024) & 0x7f) << 25);
+ printram("REFI [%x] = %x\n", 0x400 * channel + 0x4298, reg);
MCHBAR32(0x400 * channel + 0x4298) = reg;
MCHBAR32(0x400 * channel + 0x4294) |= 0xff;
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