[coreboot-gerrit] Change in coreboot[master]: soc/intel/icelake: Rename `pch_init()` function

[Angel Pons (Code Review)]

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50944 )

Change subject: soc/intel/icelake: Rename `pch_init()` function
......................................................................

soc/intel/icelake: Rename `pch_init()` function

There's two instances of the same function, one for the bootblock and
another for romstage. Prefix them with the stage they are executed in.

Change-Id: I35e87cd47f3cef8952481d25b54558a546aebb60
Signed-off-by: Angel Pons 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50944
Reviewed-by: Michael Niewöhner 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/icelake/bootblock/bootblock.c
M src/soc/intel/icelake/bootblock/pch.c
M src/soc/intel/icelake/include/soc/bootblock.h
M src/soc/intel/icelake/include/soc/romstage.h
M src/soc/intel/icelake/romstage/pch.c
M src/soc/intel/icelake/romstage/romstage.c
6 files changed, 6 insertions(+), 6 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Michael Niewöhner: Looks good to me, approved

diff --git a/src/soc/intel/icelake/bootblock/bootblock.c b/src/soc/intel/icelake/bootblock/bootblock.c
index 54ad85a..9f360da 100644
--- a/src/soc/intel/icelake/bootblock/bootblock.c
+++ b/src/soc/intel/icelake/bootblock/bootblock.c
@@ -24,5 +24,5 @@
 void bootblock_soc_init(void)
 {
    report_platform_info();
-	pch_init();
+	bootblock_pch_init();
 }
diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c
index a4166fc..7694a10 100644
--- a/src/soc/intel/icelake/bootblock/pch.c
+++ b/src/soc/intel/icelake/bootblock/pch.c
@@ -109,7 +109,7 @@
    pch_enable_lpc();
 }

-void pch_init(void)
+void bootblock_pch_init(void)
 {
    /*
     * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT,
diff --git a/src/soc/intel/icelake/include/soc/bootblock.h b/src/soc/intel/icelake/include/soc/bootblock.h
index 0132cfc..f22b266 100644
--- a/src/soc/intel/icelake/include/soc/bootblock.h
+++ b/src/soc/intel/icelake/include/soc/bootblock.h
@@ -8,7 +8,7 @@
 void bootblock_pch_early_init(void);

/* Bootblock post console init programming */
-void pch_init(void);
+void bootblock_pch_init(void);
 void pch_early_iorange_init(void);
 void report_platform_info(void);

diff --git a/src/soc/intel/icelake/include/soc/romstage.h b/src/soc/intel/icelake/include/soc/romstage.h
index 90a19f2..3772db4 100644
--- a/src/soc/intel/icelake/include/soc/romstage.h
+++ b/src/soc/intel/icelake/include/soc/romstage.h
@@ -7,7 +7,7 @@

void mainboard_memory_init_params(FSPM_UPD *mupd);
 void systemagent_early_init(void);
-void pch_init(void);
+void romstage_pch_init(void);

/* Board type */
 enum board_type {
diff --git a/src/soc/intel/icelake/romstage/pch.c b/src/soc/intel/icelake/romstage/pch.c
index e800ce5..6b134c0 100644
--- a/src/soc/intel/icelake/romstage/pch.c
+++ b/src/soc/intel/icelake/romstage/pch.c
@@ -4,7 +4,7 @@
 #include <intelblocks/tco.h>
 #include <soc/romstage.h>

-void pch_init(void)
+void romstage_pch_init(void)
 {
    /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */
    tco_configure();
diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c
index 6af2961..1517974 100644
--- a/src/soc/intel/icelake/romstage/romstage.c
+++ b/src/soc/intel/icelake/romstage/romstage.c
@@ -111,7 +111,7 @@
    /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */
    systemagent_early_init();
    /* Program PCH init */
-	pch_init();
+	romstage_pch_init();
    /* initialize Heci interface */
    heci_init(HECI1_BASE_ADDRESS);