Ravi kumar has uploaded this change for review.
sc7280: Add clock driver
Add support for clock driver for SC7280
Change-Id: I73661f709091da0a6bada43d20fb3bf4fe20b81c
---
M src/soc/qualcomm/sc7280/Makefile.inc
M src/soc/qualcomm/sc7280/bootblock.c
A src/soc/qualcomm/sc7280/clock.c
M src/soc/qualcomm/sc7280/include/soc/addressmap.h
A src/soc/qualcomm/sc7280/include/soc/clock.h
5 files changed, 548 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/47076/1
diff --git a/src/soc/qualcomm/sc7280/Makefile.inc b/src/soc/qualcomm/sc7280/Makefile.inc
index 33f6def..f94a425 100644
--- a/src/soc/qualcomm/sc7280/Makefile.inc
+++ b/src/soc/qualcomm/sc7280/Makefile.inc
@@ -7,11 +7,13 @@
bootblock-y += timer.c
bootblock-y += spi.c
bootblock-$(CONFIG_SC7280_QSPI) += qspi.c
+bootblock-y += clock.c
################################################################################
verstage-y += timer.c
verstage-y += spi.c
verstage-$(CONFIG_SC7280_QSPI) += qspi.c
+verstage-y += clock.c
################################################################################
romstage-y += cbmem.c
@@ -22,6 +24,7 @@
romstage-y += mmu.c
romstage-y += spi.c
romstage-$(CONFIG_SC7280_QSPI) += qspi.c
+romstage-y += clock.c
################################################################################
ramstage-y += soc.c
@@ -29,6 +32,7 @@
ramstage-y += timer.c
ramstage-y += spi.c
ramstage-$(CONFIG_SC7280_QSPI) += qspi.c
+ramstage-y += clock.c
################################################################################
diff --git a/src/soc/qualcomm/sc7280/bootblock.c b/src/soc/qualcomm/sc7280/bootblock.c
index 9e04351..49c9e18 100644
--- a/src/soc/qualcomm/sc7280/bootblock.c
+++ b/src/soc/qualcomm/sc7280/bootblock.c
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <bootblock_common.h>
+#include <soc/clock.h>
#include <soc/mmu.h>
#include <soc/qspi.h>
@@ -8,4 +9,5 @@
{
sc7280_mmu_init();
quadspi_init(37500 * KHz);
+ clock_init();
}
diff --git a/src/soc/qualcomm/sc7280/clock.c b/src/soc/qualcomm/sc7280/clock.c
new file mode 100644
index 0000000..f8285ba
--- /dev/null
+++ b/src/soc/qualcomm/sc7280/clock.c
@@ -0,0 +1,315 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <assert.h>
+#include <commonlib/helpers.h>
+#include <delay.h>
+#include <device/mmio.h>
+#include <soc/clock.h>
+#include <timer.h>
+#include <types.h>
+
+#define DIV(div) (2 * div - 1)
+
+struct clock_config qup_cfg[] = {
+ {
+ .hz = SRC_XO_HZ, /* 19.2KHz */
+ .src = SRC_XO_19_2MHZ,
+ .div = DIV(1),
+ }
+};
+
+struct clock_config qspi_core_cfg[] = {
+ {
+ .hz = SRC_XO_HZ, /* 19.2KHz */
+ .src = SRC_XO_19_2MHZ,
+ .div = DIV(1),
+ },
+ {
+ .hz = 100 * MHz,
+ .src = SRC_GPLL0_MAIN_600MHZ,
+ .div = DIV(6),
+ },
+ {
+ .hz = 200 * MHz,
+ .src = SRC_GPLL0_MAIN_600MHZ,
+ .div = DIV(3),
+ },
+ {
+ .hz = 400 * MHz,
+ .src = SRC_GPLL0_MAIN_600MHZ,
+ .div = DIV(1.5),
+ },
+};
+
+struct clock_config qup_wrap_cfg[] = {
+ {
+ .hz = SRC_XO_HZ, /* 19.2KHz */
+ .src = SRC_XO_19_2MHZ,
+ .div = DIV(1),
+ },
+ {
+ .hz = 32 * MHz,
+ .src = SRC_GPLL0_EVEN_300MHZ,
+ .div = DIV(1),
+ .m = 8,
+ .n = 75,
+ .d_2 = 75,
+ },
+ {
+ .hz = 48 * MHz,
+ .src = SRC_GPLL0_EVEN_300MHZ,
+ .div = DIV(1),
+ .m = 4,
+ .n = 25,
+ .d_2 = 25,
+ },
+ {
+ .hz = 64 * MHz,
+ .src = SRC_GPLL0_EVEN_300MHZ,
+ .div = DIV(1),
+ .m = 16,
+ .n = 75,
+ .d_2 = 75,
+ },
+ {
+ .hz = 96 * MHz,
+ .src = SRC_GPLL0_EVEN_300MHZ,
+ .div = DIV(1),
+ .m = 8,
+ .n = 25,
+ .d_2 = 25,
+ },
+ {
+ .hz = 100 * MHz,
+ .src = SRC_GPLL0_MAIN_600MHZ,
+ .div = DIV(6),
+ },
+ {
+ .hz = SRC_XO_HZ, /* 19.2KHz */
+ .src = SRC_XO_19_2MHZ,
+ .div = DIV(1),
+ },
+ {
+ .hz = SRC_XO_HZ, /* 19.2KHz */
+ .src = SRC_XO_19_2MHZ,
+ .div = DIV(1),
+ },
+};
+
+static int clock_configure_gpll0(void)
+{
+ clrbits32(&gcc->gpll0.config_ctl_u1,
+ BIT(CLK_CTL_GPLL_BB_CAL_CORR_INDEX_SHFT));
+ setbits32(&gcc->gpll0.config_ctl_u1,
+ BIT(CLK_CTL_GPLL_PCODE_OFFET_28) |
+ BIT(CLK_CTL_GPLL_PCODE_OFFET_29));
+
+ /* Keep existing GPLL0 configuration, in RUN mode @600Mhz. */
+ setbits32(&gcc->gpll0.user_ctl,
+ 1 << CLK_CTL_GPLL_PLLOUT_EVEN_SHFT |
+ 1 << CLK_CTL_GPLL_PLLOUT_MAIN_SHFT |
+ 1 << CLK_CTL_GPLL_PLLOUT_ODD_SHFT);
+
+ return CB_SUCCESS;
+}
+
+static int clock_configure_mnd(struct sc7280_clock *clk, uint32_t m, uint32_t n,
+ uint32_t d_2)
+{
+ struct sc7280_mnd_clock *mnd = (struct sc7280_mnd_clock *)clk;
+ setbits32(&clk->rcg_cfg,
+ RCG_MODE_DUAL_EDGE << CLK_CTL_CFG_MODE_SHFT);
+
+ write32(&mnd->m, m & CLK_CTL_RCG_MND_BMSK);
+ write32(&mnd->n, ~(n-m) & CLK_CTL_RCG_MND_BMSK);
+ write32(&mnd->d_2, ~(d_2) & CLK_CTL_RCG_MND_BMSK);
+
+ return CB_SUCCESS;
+}
+
+static int clock_configure(struct sc7280_clock *clk,
+ struct clock_config *clk_cfg,
+ uint32_t hz, uint32_t num_perfs)
+{
+ uint32_t reg_val;
+ uint32_t idx;
+
+ for (idx = 0; idx < num_perfs; idx++)
+ if (hz <= clk_cfg[idx].hz)
+ break;
+
+ assert(hz == clk_cfg[idx].hz);
+
+ reg_val = (clk_cfg[idx].src << CLK_CTL_CFG_SRC_SEL_SHFT) |
+ (clk_cfg[idx].div << CLK_CTL_CFG_SRC_DIV_SHFT);
+
+ /* Set clock config */
+ write32(&clk->rcg_cfg, reg_val);
+
+ if (clk_cfg[idx].m != 0)
+ clock_configure_mnd(clk, clk_cfg[idx].m, clk_cfg[idx].n,
+ clk_cfg[idx].d_2);
+
+ /* Commit config to RCG*/
+ setbits32(&clk->rcg_cmd, BIT(CLK_CTL_CMD_UPDATE_SHFT));
+
+ return CB_SUCCESS;
+}
+
+static bool clock_is_off(u32 *cbcr_addr)
+{
+ return (read32(cbcr_addr) & CLK_CTL_CBC_CLK_OFF_BMSK);
+}
+
+static int clock_enable_vote(void *cbcr_addr, void *vote_addr,
+ uint32_t vote_bit)
+{
+ int count = 200;
+
+ /* Set clock vote bit */
+ setbits32(vote_addr, BIT(vote_bit));
+
+ /* Ensure clock is enabled */
+ while (count-- > 0) {
+ if (!clock_is_off(cbcr_addr))
+ return CB_SUCCESS;
+ udelay(1);
+ }
+ return CB_ERR;
+}
+
+static int clock_enable(void *cbcr_addr)
+{
+ int count = 200;
+
+ /* Set clock enable bit */
+ setbits32(cbcr_addr, BIT(CLK_CTL_CBC_CLK_EN_SHFT));
+
+ /* Ensure clock is enabled */
+ while (count-- > 0) {
+ if (!clock_is_off(cbcr_addr))
+ return CB_SUCCESS;
+ udelay(1);
+ }
+ return CB_ERR;
+}
+
+void clock_reset_aop(void)
+{
+ /* Bring AOP out of RESET */
+ clrbits32(&aoss->aoss_cc_apcs_misc, BIT(AOP_RESET_SHFT));
+}
+
+void clock_configure_qspi(uint32_t hz)
+{
+ clock_configure(&gcc->qspi_core,
+ qspi_core_cfg, hz,
+ ARRAY_SIZE(qspi_core_cfg));
+ clock_enable(&gcc->qspi_cnoc_ahb_cbcr);
+ clock_enable(&gcc->qspi_core_cbcr);
+}
+
+int clock_reset_bcr(void *bcr_addr, bool reset)
+{
+ struct sc7280_bcr *bcr = bcr_addr;
+
+ if (reset)
+ setbits32(bcr, BIT(CLK_CTL_BCR_BLK_SHFT));
+ else
+ clrbits32(bcr, BIT(CLK_CTL_BCR_BLK_SHFT));
+
+ return CB_SUCCESS;
+}
+
+void clock_configure_dfsr(int qup)
+{
+ int idx;
+ int s = qup % QUP_WRAP1_S0;
+ uint32_t reg_val;
+ struct sc7280_qupv3_clock *qup_clk = qup < QUP_WRAP1_S0 ?
+ &gcc->qup_wrap0_s[s] : &gcc->qup_wrap1_s[s];
+
+ clrsetbits32(&qup_clk->dfsr_clk.cmd_dfsr,
+ BIT(CLK_CTL_CMD_RCG_SW_CTL_SHFT),
+ BIT(CLK_CTL_CMD_DFSR_SHFT));
+
+ for (idx = 0; idx < ARRAY_SIZE(qup_wrap_cfg); idx++) {
+ reg_val = (qup_wrap_cfg[idx].src << CLK_CTL_CFG_SRC_SEL_SHFT) |
+ (qup_wrap_cfg[idx].div << CLK_CTL_CFG_SRC_DIV_SHFT);
+
+ write32(&qup_clk->dfsr_clk.perf_dfsr[idx], reg_val);
+
+ if (qup_wrap_cfg[idx].m == 0)
+ continue;
+
+ setbits32(&qup_clk->dfsr_clk.perf_dfsr[idx],
+ RCG_MODE_DUAL_EDGE << CLK_CTL_CFG_MODE_SHFT);
+
+ reg_val = qup_wrap_cfg[idx].m & CLK_CTL_RCG_MND_BMSK;
+ write32(&qup_clk->dfsr_clk.perf_m_dfsr[idx], reg_val);
+
+ reg_val = ~(qup_wrap_cfg[idx].n - qup_wrap_cfg[idx].m)
+ & CLK_CTL_RCG_MND_BMSK;
+ write32(&qup_clk->dfsr_clk.perf_n_dfsr[idx], reg_val);
+
+ reg_val = ~(qup_wrap_cfg[idx].d_2) & CLK_CTL_RCG_MND_BMSK;
+ write32(&qup_clk->dfsr_clk.perf_d_dfsr[idx], reg_val);
+ }
+}
+
+void clock_configure_qup(int qup, uint32_t hz)
+{
+ int s = qup % QUP_WRAP1_S0;
+ struct sc7280_qupv3_clock *qup_clk = qup < QUP_WRAP1_S0 ?
+ &gcc->qup_wrap0_s[s] : &gcc->qup_wrap1_s[s];
+
+ clock_configure(&qup_clk->mnd_clk.clock, qup_cfg, hz,
+ ARRAY_SIZE(qup_cfg));
+}
+
+void clock_enable_qup(int qup)
+{
+ int s = qup % QUP_WRAP1_S0;
+ int clk_en_off = qup < QUP_WRAP1_S0 ?
+ QUPV3_WRAP0_CLK_ENA_S(s) : QUPV3_WRAP1_CLK_ENA_S(s);
+ struct sc7280_qupv3_clock *qup_clk = qup < QUP_WRAP1_S0 ?
+ &gcc->qup_wrap0_s[s] : &gcc->qup_wrap1_s[s];
+
+ if(qup == 14 || qup == 15)
+ clock_enable_vote(&qup_clk->mnd_clk, &gcc->apcs_clk_br_en,
+ (qup-1));
+ else
+ clock_enable_vote(&qup_clk->mnd_clk, &gcc->apcs_clk_br_en1,
+ clk_en_off);
+}
+
+void clock_init(void)
+{
+ clock_configure_gpll0();
+
+ clock_enable_vote(&gcc->qup_wrap0_core_2x_cbcr,
+ &gcc->apcs_clk_br_en1,
+ QUPV3_WRAP0_CORE_2X_CLK_ENA);
+ clock_enable_vote(&gcc->qup_wrap0_core_cbcr,
+ &gcc->apcs_clk_br_en1,
+ QUPV3_WRAP0_CORE_CLK_ENA);
+ clock_enable_vote(&gcc->qup_wrap0_m_ahb_cbcr,
+ &gcc->apcs_clk_br_en1,
+ QUPV3_WRAP_0_M_AHB_CLK_ENA);
+ clock_enable_vote(&gcc->qup_wrap0_s_ahb_cbcr,
+ &gcc->apcs_clk_br_en1,
+ QUPV3_WRAP_0_S_AHB_CLK_ENA);
+
+ clock_enable_vote(&gcc->qup_wrap1_core_2x_cbcr,
+ &gcc->apcs_clk_br_en1,
+ QUPV3_WRAP1_CORE_2X_CLK_ENA);
+ clock_enable_vote(&gcc->qup_wrap1_core_cbcr,
+ &gcc->apcs_clk_br_en1,
+ QUPV3_WRAP1_CORE_CLK_ENA);
+ clock_enable_vote(&gcc->qup_wrap1_m_ahb_cbcr,
+ &gcc->apcs_clk_br_en1,
+ QUPV3_WRAP_1_M_AHB_CLK_ENA);
+ clock_enable_vote(&gcc->qup_wrap1_s_ahb_cbcr,
+ &gcc->apcs_clk_br_en1,
+ QUPV3_WRAP_1_S_AHB_CLK_ENA);
+}
diff --git a/src/soc/qualcomm/sc7280/include/soc/addressmap.h b/src/soc/qualcomm/sc7280/include/soc/addressmap.h
index 70d17be..ae31b1c 100644
--- a/src/soc/qualcomm/sc7280/include/soc/addressmap.h
+++ b/src/soc/qualcomm/sc7280/include/soc/addressmap.h
@@ -5,4 +5,8 @@
#include <stdint.h>
+#define AOSS_CC_BASE 0x0C2A0000
+#define GCC_BASE 0x00100000
+#define QSPI_BASE 0x088DC000
+
#endif /* __SOC_QUALCOMM_SC7280_ADDRESS_MAP_H__ */
diff --git a/src/soc/qualcomm/sc7280/include/soc/clock.h b/src/soc/qualcomm/sc7280/include/soc/clock.h
new file mode 100644
index 0000000..947f262
--- /dev/null
+++ b/src/soc/qualcomm/sc7280/include/soc/clock.h
@@ -0,0 +1,223 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/addressmap.h>
+#include <types.h>
+
+#ifndef __SOC_QUALCOMM_SC7280_CLOCK_H__
+#define __SOC_QUALCOMM_SC7280_CLOCK_H__
+
+#define QUPV3_WRAP_0_M_AHB_CLK_ENA 6
+#define QUPV3_WRAP_0_S_AHB_CLK_ENA 7
+#define QUPV3_WRAP0_CORE_2X_CLK_ENA 9
+#define QUPV3_WRAP0_CORE_CLK_ENA 8
+#define QUPV3_WRAP1_CORE_2X_CLK_ENA 18
+#define QUPV3_WRAP1_CORE_CLK_ENA 19
+#define QUPV3_WRAP_1_M_AHB_CLK_ENA 20
+#define QUPV3_WRAP_1_S_AHB_CLK_ENA 21
+#define QUPV3_WRAP0_CLK_ENA_S(idx) (10 + idx)
+#define QUPV3_WRAP1_CLK_ENA_S(idx) (22 + idx)
+
+#define SRC_XO_HZ (19200 * KHz)
+#define GPLL0_EVEN_HZ (300 * MHz)
+#define GPLL0_MAIN_HZ (600 * MHz)
+
+#define SRC_XO_19_2MHZ 0
+#define SRC_GPLL0_MAIN_600MHZ 1
+#define SRC_GPLL0_EVEN_300MHZ 6
+
+#define AOP_RESET_SHFT 0
+#define RCG_MODE_DUAL_EDGE 2
+
+#define SCALE_FREQ_SHFT 11
+
+struct sc7280_clock {
+ u32 rcg_cmd;
+ u32 rcg_cfg;
+};
+
+struct sc7280_mnd_clock {
+ struct sc7280_clock clock;
+ u32 m;
+ u32 n;
+ u32 d_2;
+};
+
+struct sc7280_dfsr_clock {
+ u32 cmd_dfsr;
+ u8 _res0[0x20 - 0x1c];
+ u32 perf_dfsr[8];
+ u8 _res1[0x60 - 0x40];
+ u32 perf_m_dfsr[8];
+ u8 _res2[0xa0 - 0x80];
+ u32 perf_n_dfsr[8];
+ u8 _res3[0xe0 - 0xc0];
+ u32 perf_d_dfsr[8];
+ u8 _res4[0x130 - 0x100];
+};
+
+struct sc7280_qupv3_clock {
+ u32 cbcr;
+ struct sc7280_mnd_clock mnd_clk;
+ struct sc7280_dfsr_clock dfsr_clk;
+};
+
+struct sc7280_gpll {
+ u32 mode;
+ u32 l_val;
+ u32 cal_l_val;
+ u32 user_ctl;
+ u32 user_ctl_u;
+ u32 user_Ctl_u1;
+ u32 config_ctl;
+ u32 config_ctl_u;
+ u32 config_ctl_u1;
+ u32 test_ctl;
+ u32 test_ctl_u;
+ u32 test_ctl_u1;
+ u8 _res[0x1000 - 0x30];
+};
+
+struct sc7280_gcc {
+ struct sc7280_gpll gpll0;
+ u8 _res1[0x17000 - 0x1000];
+ u32 qup_wrap0_bcr;
+ u32 qup_wrap0_m_ahb_cbcr;
+ u32 qup_wrap0_s_ahb_cbcr;
+ struct sc7280_qupv3_clock qup_wrap0_s[8];
+ u8 _res3[0x18000 - 0x1798c];
+ u32 qup_wrap1_bcr;
+ u32 qup_wrap1_m_ahb_cbcr;
+ u32 qup_wrap1_s_ahb_cbcr;
+ struct sc7280_qupv3_clock qup_wrap1_s[8];
+ u8 _res4[0x23000 - 0x1898c];
+ u32 qup_wrap0_core_cbcr;
+ u32 qup_wrap0_core_cdivr;
+ u32 qup_wrap0_core_2x_cbcr;
+ struct sc7280_clock qup_wrap0_core_2x;
+ u8 _res5[0x23138 - 0x23014];
+ u32 qup_wrap1_core_cbcr;
+ u32 qup_wrap1_core_cdivr;
+ u32 qup_wrap1_core_2x_cbcr;
+ struct sc7280_clock qup_wrap1_core_2x;
+ u8 _res6[0x4b000 - 0x2314c];
+ u32 qspi_bcr;
+ u32 qspi_cnoc_ahb_cbcr;
+ u32 qspi_core_cbcr;
+ struct sc7280_clock qspi_core;
+ u8 _res7[0x52000 - 0x4b014];
+ u32 apcs_clk_br_en;
+ u8 _res8[0x52008 - 0x52004];
+ u32 apcs_clk_br_en1;
+ u8 _res9[0x1000000 - 0x5200c];
+};
+check_member(sc7280_gcc, qup_wrap0_bcr, 0x17000);
+check_member(sc7280_gcc, qup_wrap1_bcr, 0x18000);
+check_member(sc7280_gcc, qup_wrap1_core_cbcr, 0x23138);
+check_member(sc7280_gcc, apcs_clk_br_en1, 0x52008);
+
+struct sc7280_aoss {
+ u8 _res0[0x50020];
+ u32 aoss_cc_reset_status;
+ u8 _res1[0x5002C - 0x50024];
+ u32 aoss_cc_apcs_misc;
+};
+check_member(sc7280_aoss, aoss_cc_reset_status, 0x50020);
+check_member(sc7280_aoss, aoss_cc_apcs_misc, 0x5002C);
+
+enum clk_ctl_gpll_user_ctl {
+ CLK_CTL_GPLL_PLLOUT_EVEN_BMSK = 0x2,
+ CLK_CTL_GPLL_PLLOUT_MAIN_SHFT = 0,
+ CLK_CTL_GPLL_PLLOUT_EVEN_SHFT = 1,
+ CLK_CTL_GPLL_PLLOUT_ODD_SHFT = 2
+};
+
+enum clk_ctl_gpll_config_ctl {
+ CLK_CTL_GPLL_BB_CAL_CORR_INDEX_SHFT = 14,
+ CLK_CTL_GPLL_PCODE_OFFET_28 = 28,
+ CLK_CTL_GPLL_PCODE_OFFET_29 = 29,
+};
+
+enum clk_ctl_cfg_rcgr {
+ CLK_CTL_CFG_HW_CTL_BMSK = 0x100000,
+ CLK_CTL_CFG_HW_CTL_SHFT = 20,
+ CLK_CTL_CFG_MODE_BMSK = 0x3000,
+ CLK_CTL_CFG_MODE_SHFT = 12,
+ CLK_CTL_CFG_SRC_SEL_BMSK = 0x700,
+ CLK_CTL_CFG_SRC_SEL_SHFT = 8,
+ CLK_CTL_CFG_SRC_DIV_BMSK = 0x1F,
+ CLK_CTL_CFG_SRC_DIV_SHFT = 0
+};
+
+enum clk_ctl_cmd_rcgr {
+ CLK_CTL_CMD_ROOT_OFF_BMSK = 0x80000000,
+ CLK_CTL_CMD_ROOT_OFF_SHFT = 31,
+ CLK_CTL_CMD_ROOT_EN_BMSK = 0x2,
+ CLK_CTL_CMD_ROOT_EN_SHFT = 1,
+ CLK_CTL_CMD_UPDATE_BMSK = 0x1,
+ CLK_CTL_CMD_UPDATE_SHFT = 0
+};
+
+enum clk_ctl_cbcr {
+ CLK_CTL_CBC_CLK_OFF_BMSK = 0x80000000,
+ CLK_CTL_CBC_CLK_OFF_SHFT = 31,
+ CLK_CTL_CBC_CLK_EN_BMSK = 0x1,
+ CLK_CTL_CBC_CLK_EN_SHFT = 0
+};
+
+enum clk_ctl_rcg_mnd {
+ CLK_CTL_RCG_MND_BMSK = 0xFFFF,
+ CLK_CTL_RCG_MND_SHFT = 0,
+};
+
+enum clk_ctl_bcr {
+ CLK_CTL_BCR_BLK_BMSK = 0x1,
+ CLK_CTL_BCR_BLK_SHFT = 0,
+};
+
+enum clk_ctl_dfsr {
+ CLK_CTL_CMD_DFSR_BMSK = 0x1,
+ CLK_CTL_CMD_DFSR_SHFT = 0,
+ CLK_CTL_CMD_RCG_SW_CTL_SHFT = 15,
+};
+
+enum clk_qup {
+ QUP_WRAP0_S0,
+ QUP_WRAP0_S1,
+ QUP_WRAP0_S2,
+ QUP_WRAP0_S3,
+ QUP_WRAP0_S4,
+ QUP_WRAP0_S5,
+ QUP_WRAP0_S6,
+ QUP_WRAP0_S7,
+ QUP_WRAP1_S0,
+ QUP_WRAP1_S1,
+ QUP_WRAP1_S2,
+ QUP_WRAP1_S3,
+ QUP_WRAP1_S4,
+ QUP_WRAP1_S5,
+ QUP_WRAP1_S6,
+ QUP_WRAP1_S7,
+};
+
+struct clock_config {
+ uint32_t hz;
+ uint8_t src;
+ uint8_t div;
+ uint16_t m;
+ uint16_t n;
+ uint16_t d_2;
+};
+
+static struct sc7280_gcc *const gcc = (void *)GCC_BASE;
+static struct sc7280_aoss *const aoss = (void *)AOSS_CC_BASE;
+
+void clock_init(void);
+void clock_reset_aop(void);
+void clock_configure_qspi(uint32_t hz);
+int clock_reset_bcr(void *bcr_addr, bool reset);
+void clock_configure_qup(int qup, uint32_t hz);
+void clock_enable_qup(int qup);
+void clock_configure_dfsr(int qup);
+void clock_last_reset_was_watchdog(void);
+
+#endif // __SOC_QUALCOMM_SC7280_CLOCK_H__
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