Lijian Zhao has uploaded this change for review.
soc/intel/common: Limit BIOS region cache to 16MB
Cache BIOS region can boost boot performance, however it can't be over
16MB, according to processor EDS vol1, FLASH+APIC LT will be less than
20MB under 4G. Set the maxiam to 16GB to save numbers of mtrr entries.
BUG=b:119267832
TEST=Build and boot up fine on whiskeylake rvp platform.
Change-Id: I46a47c8bf66b14fb2fcb7b6b1d30d02886c450a4
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
---
M src/soc/intel/common/block/fast_spi/fast_spi.c
1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/29944/1
diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c
index 5ff0872..8649f0c 100644
--- a/src/soc/intel/common/block/fast_spi/fast_spi.c
+++ b/src/soc/intel/common/block/fast_spi/fast_spi.c
@@ -240,6 +240,10 @@
if (!bios_size)
return;
+ /* Cache up to 16MB to boost boot performace */
+ if (bios_size > 16 * MiB)
+ bios_size = 16 * MiB;
+
/* Round to power of two */
alignment = 1UL << (log2_ceil(bios_size));
bios_size = ALIGN_UP(bios_size, alignment);
To view, visit change 29944. To unsubscribe, or for help writing mail filters, visit settings.