Patch Set #7, Line 27:
This is not sufficient. When CAR is active it's microarchitecturally defined how a clflush is handled in CAR mode. You need a way for the chipset to indicate this is valid sequence that can be performed.
This seems to work for Intel CPUs with a NEM and also older ones lacking it. Subrata tested a similar concept with WB caching cbmem on much more recent Intel CPU's (probably NEM enhanced). So at first sight it looks like this will be ok for most Intel? Probably worth checking for some AMD.
Those results are clearly empirical which suggests that the chipsets need to opt-in to affirm this will work.
> Aren't there defines for these bits instead of open coding them? […]
Can you start?
Patch Set #7, Line 60:
Why is a cbmem check in here? It doesn't immediately make sense why this would be the case. Likewise, this function is also active when not loading postcar, e.g. FSP. What about that? Or are you using cbmem to be an indirect proxy for postcar loading?
It wanted to use that as proxy that dram is ready and avoid it when things are loaded into CAR like FSP (if non-XIP). Is checking for [start, start + size] being inside the CAR region sufficient/better?
If that's the case then please comment the purpose of what the check is for. It's clearly indirect w.r.t. to what you want accomplish from your explanation.
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