Timothy Pearson (tpearson@raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12049 -gerrit commit 13a63340fc69c562d5acfb9b1b128108bb24c033 Author: Timothy Pearson <tpearson@raptorengineeringinc.com> Date: Fri Aug 14 02:50:44 2015 -0500 southbridge/amd/sr5650: Use correct PCI configuration block offset Change-Id: I4277d1788d8f9a501399218544aa6d4d11349ccc Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> --- src/southbridge/amd/sr5650/acpi/sr5650.asl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/southbridge/amd/sr5650/acpi/sr5650.asl b/src/southbridge/amd/sr5650/acpi/sr5650.asl index 54259b0..93a74e3 100644 --- a/src/southbridge/amd/sr5650/acpi/sr5650.asl +++ b/src/southbridge/amd/sr5650/acpi/sr5650.asl @@ -15,8 +15,8 @@ */ Scope(\) { - Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ - Name(HPBA, 0xFED00000) /* Base address of HPET table */ + Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ + Name(HPBA, 0xFED00000) /* Base address of HPET table */ /* PIC IRQ mapping registers, C00h-C01h */ OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)