Karthik Ramasubramanian uploaded patch set #5 to the change originally created by Tim Wawrzynczak.

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soc/intel/tigerlake: Add PCH PCIe RPs wake up events to event log

All wakes by a PCH PCIe root port were lumped under one event source;
this commit splits them up so each root port gets its own ID in the
event log.

BUG=b:172279061
BRANCH=volteer

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Icebcac3b69c605ecf6df37733b641397ea3c3ad0
---
M src/soc/intel/tigerlake/elog.c
1 file changed, 41 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/47182/5

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Icebcac3b69c605ecf6df37733b641397ea3c3ad0
Gerrit-Change-Number: 47182
Gerrit-PatchSet: 5
Gerrit-Owner: Tim Wawrzynczak <twawrzynczak@chromium.org>
Gerrit-Reviewer: Furquan Shaikh <furquan@google.com>
Gerrit-Reviewer: Karthik Ramasubramanian <kramasub@google.com>
Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>
Gerrit-MessageType: newpatchset