You can ignore the bikeshedding comments, that was before
I looked into the documentation. It seems the SDM is still
talking about Pentium4 style Hyper-Threading.
Starting with Nehalem, their second HT incarnation, I
see the requirement to do it on all logical processors
with synchronisation per core.
Starting with Ivy Bridge, the synchronisation requirement
vanished.
@Intel, please assist to get the Software Developer's
Manual updated (or the BWGs fixed if they are wrong).
Patch set 2:Code-Review -1
4 comments:
File src/soc/intel/common/block/cpu/mp_init.c:
CPU, at least to me, usually refers to the whole package.
253668-060US
* Intel SDM Chapter 9.11.6.3
A much better reference would be the name of the document and the
chapter. Chapter numbers change, and even if one knows the document
revision that doesn't mean they have access to that specific revision.
* "Update in a System Supporting Intel Hyper-Threading Technology"
* Intel Hyper-Threading Technology has implications on the loading of the
* microcode update. The update must be loaded for each core in a physical
* processor. Thus, for a processor supporting Intel Hyper-Threading
* Technology, only one logical processor per core is required to load the
* microcode update. Each individual logical processor can independently
* load the update. However, MP initialization must provide some mechanism
* (e.g. a software semaphore) to force serialization of microcode update
* loads and to prevent simultaneous load attempts to the same core.
No need for the quote, imho.
Patch Set #2, Line 162: /* Update microcode on BSP */
That's obvious. Much more interesting would be to know why?
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