Sukumar Ghorai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78177?usp=email )
Change subject: soc/intel: Fix cpu-pc10 residency counter frequency in LPIT table ......................................................................
soc/intel: Fix cpu-pc10 residency counter frequency in LPIT table
Intel platforms use Low Power Idle Table(LPIT) to enumerate platform Low Power Idle states. There are two types of low power residencies a) CPU PKG C10 - read via MSR (Function fixed hardware interface) b) Platform Controller Hub (PCH) SLP_S0 - read via memory mapped
Ref. https://www.uefi.org/sites/default/files/resources/ Intel_ACPI_Low_Power_S0_Idle.pdf, section 2.2.1: value of 0 indicates that counter runs at TSC frequency.
Ref. Intel® 64 and IA-32 Architectures Software Developer’s Manual (Vol 4) MSR 0x632: PC10 residency counter is at same frequency as the TSC.
BUG=b:300440936 TEST=check kernel cpuidle sysfs for sleep residency cat /sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us
Change-Id: Ibde764551a21b9aecb1c269948f4823548294711 Signed-off-by: Sukumar Ghorai sukumar.ghorai@intel.com --- M src/soc/intel/common/block/acpi/lpit.c 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/78177/1
diff --git a/src/soc/intel/common/block/acpi/lpit.c b/src/soc/intel/common/block/acpi/lpit.c index 38a402f..3d22f4a 100644 --- a/src/soc/intel/common/block/acpi/lpit.c +++ b/src/soc/intel/common/block/acpi/lpit.c @@ -31,7 +31,7 @@ pkg_counter->residency_counter.bit_width = 64; pkg_counter->residency_counter.space_id = ACPI_ADDRESS_SPACE_FIXED; pkg_counter->residency_counter.access_size = ACPI_ACCESS_SIZE_UNDEFINED; - pkg_counter->counter_frequency = ACPI_LPIT_CTR_FREQ_TSC; + pkg_counter->counter_frequency = 0; /* same freq as TSC */
/* Min. residency and worst-case latency (from FSP and vendor dumps) */ pkg_counter->min_residency = 30000; /* break-even: 30 ms */