Attention is currently required from: Felix Singer, Nick Vaccaro.

Felix Singer uploaded patch set #2 to this change.

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The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins)

intel tgl mainboards: Move PcieRpEnable option below dt entries

There is work being done on better integrating the root port entries
from the devicetree by hooking up the FSP option PcieRpEnable to them,
which supersedes the devicetree option.

Move the PcieRpEnable option below their related devicetree entries in
order to make the review easier when the option is removed. Create
devicetree entries in case of they don't exist yet.

Change-Id: I65bf27342191129b433d779774e084eecb4e4b3e
Signed-off-by: Felix Singer <felixsinger@posteo.net>
---
M src/mainboard/google/volteer/variants/baseboard/devicetree.cb
M src/mainboard/google/volteer/variants/chronicler/overridetree.cb
M src/mainboard/google/volteer/variants/elemi/overridetree.cb
M src/mainboard/google/volteer/variants/voema/overridetree.cb
M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
6 files changed, 46 insertions(+), 31 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/79960/2

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Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I65bf27342191129b433d779774e084eecb4e4b3e
Gerrit-Change-Number: 79960
Gerrit-PatchSet: 2
Gerrit-Owner: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Gerrit-Reviewer: Matt DeVillier <matt.devillier@gmail.com>
Gerrit-Reviewer: Nick Vaccaro <nvaccaro@chromium.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>
Gerrit-Attention: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Gerrit-Attention: Nick Vaccaro <nvaccaro@chromium.org>
Gerrit-MessageType: newpatchset