Jonathan Neuschäfer (j.neuschaefer@gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14981
-gerrit
commit 5a9de06004bcc685ce5655eed89b1b41d7171cff Author: Jonathan Neuschäfer j.neuschaefer@gmx.net Date: Fri May 27 09:05:02 2016 +0200
[UNVERIFIED] mb/emulation/*-riscv: Use new "mipi" CSR name
I don't know the exact semantics, because the Privileged Spec 1.9 (which defines this CSR) hasn't been publicly released yet.
Change-Id: Ice369536d8ae9f46797b9f936f45ed6d7c511de6 Signed-off-by: Jonathan Neuschäfer j.neuschaefer@gmx.net --- src/mainboard/emulation/qemu-riscv/qemu_util.c | 2 +- src/mainboard/emulation/spike-riscv/spike_util.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mainboard/emulation/qemu-riscv/qemu_util.c b/src/mainboard/emulation/qemu-riscv/qemu_util.c index fca7d56..41a5d62 100644 --- a/src/mainboard/emulation/qemu-riscv/qemu_util.c +++ b/src/mainboard/emulation/qemu-riscv/qemu_util.c @@ -60,7 +60,7 @@ uintptr_t mcall_send_ipi(uintptr_t recipient)
if (atomic_swap(&OTHER_HLS(recipient)->ipi_pending, 1) == 0) { mb(); - write_csr(send_ipi, recipient); + write_csr(mipi, recipient); }
return 0; diff --git a/src/mainboard/emulation/spike-riscv/spike_util.c b/src/mainboard/emulation/spike-riscv/spike_util.c index fca7d56..41a5d62 100644 --- a/src/mainboard/emulation/spike-riscv/spike_util.c +++ b/src/mainboard/emulation/spike-riscv/spike_util.c @@ -60,7 +60,7 @@ uintptr_t mcall_send_ipi(uintptr_t recipient)
if (atomic_swap(&OTHER_HLS(recipient)->ipi_pending, 1) == 0) { mb(); - write_csr(send_ipi, recipient); + write_csr(mipi, recipient); }
return 0;