Frank Wu has uploaded this change for review.

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mb/google/volteer/halvor: Update settings for audio function

Configure gpio/overridetree settings for audio function.

BUG=b:153680359, b:163382106
TEST=FW_NAME=halvor emerge-volteer coreboot chromeos-bootimage

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I107f6fc21b99d80d69931139dc50e7d5873a8e52
---
M src/mainboard/google/volteer/variants/halvor/gpio.c
M src/mainboard/google/volteer/variants/halvor/overridetree.cb
2 files changed, 9 insertions(+), 8 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/44409/1
diff --git a/src/mainboard/google/volteer/variants/halvor/gpio.c b/src/mainboard/google/volteer/variants/halvor/gpio.c
index 2a98688..92e33ca 100644
--- a/src/mainboard/google/volteer/variants/halvor/gpio.c
+++ b/src/mainboard/google/volteer/variants/halvor/gpio.c
@@ -53,6 +53,10 @@
PAD_NC(GPP_C11, NONE),
/* C13 : UART1_TXD ==> NC */
PAD_NC(GPP_C13, NONE),
+ /* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */
+ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
+ /* C17 : I2C0_SCL ==> PCH_I2C0_1V8_AUDIO_SCL */
+ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),

/* D7 : SRCCLKREQ2# ==> NC */
PAD_NC(GPP_D7, NONE),
@@ -141,6 +145,10 @@
PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2),
/* S5 : SNDW2_DATA ==> SOC_DMIC_DATA1 */
PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2),
+ /* S6 : SNDW3_CLK ==> DMIC_CLK0 */
+ PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2),
+ /* S7 : SNDW3_DATA ==> DMIC_DATA0 */
+ PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2),

/* GPD11: LANPHYC ==> NC */
PAD_NC(GPD11, NONE),
diff --git a/src/mainboard/google/volteer/variants/halvor/overridetree.cb b/src/mainboard/google/volteer/variants/halvor/overridetree.cb
index 12e059c..268b1a5 100644
--- a/src/mainboard/google/volteer/variants/halvor/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/halvor/overridetree.cb
@@ -121,13 +121,6 @@
device i2c 15 on end
end
end # I2C5 0xA0C6
- device pci 1f.3 on
- chip drivers/generic/max98357a
- register "hid" = ""MX98357A""
- register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F18)"
- register "sdmode_delay" = "5"
- device generic 0 on end
- end
- end # Intel HD audio 0xA0C8-A0CF
+ device pci 1f.3 on end # Intel HD audio 0xA0C8-A0CF
end
end

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I107f6fc21b99d80d69931139dc50e7d5873a8e52
Gerrit-Change-Number: 44409
Gerrit-PatchSet: 1
Gerrit-Owner: Frank Wu <frank_wu@compal.corp-partner.google.com>
Gerrit-MessageType: newchange