Bernardo Perez Priego has uploaded this change for review.
soc/intel/skylake: Add romstage common stage file
Change-Id: I31dc5baca23c3d339fbe5fb06b8049789d9ba415
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
---
M src/soc/intel/skylake/Kconfig
M src/soc/intel/skylake/Makefile.inc
M src/soc/intel/skylake/include/soc/romstage.h
M src/soc/intel/skylake/romstage/Makefile.inc
D src/soc/intel/skylake/romstage/pch.c
M src/soc/intel/skylake/romstage/romstage.c
6 files changed, 13 insertions(+), 29 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/42213/1
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 27c1084..c7b61bd 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -81,6 +81,8 @@
select TSC_SYNC_MFENCE
select UDELAY_TSC
select UDK_2015_BINDING
+ select SOC_INTEL_COMMON_BASECODE
+ select SOC_INTEL_COMMON_BASECODE_ROMSTAGE
config FSP_HYPERTHREADING
bool "Enable Hyper-Threading"
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index 75121ab..ee81567 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -106,6 +106,7 @@
CPPFLAGS_common += -I$(src)/soc/intel/skylake
CPPFLAGS_common += -I$(src)/soc/intel/skylake/include
+CPPFLAGS_common += -I$(src)/soc/intel/common/basecode/include
# Currently used for microcode path.
CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(MAINBOARDDIR)
diff --git a/src/soc/intel/skylake/include/soc/romstage.h b/src/soc/intel/skylake/include/soc/romstage.h
index b9eea98..cb11f50 100644
--- a/src/soc/intel/skylake/include/soc/romstage.h
+++ b/src/soc/intel/skylake/include/soc/romstage.h
@@ -7,7 +7,6 @@
void mainboard_memory_init_params(FSPM_UPD *mupd);
void systemagent_early_init(void);
-void romstage_pch_init(void);
int smbus_read_byte(unsigned int device, unsigned int address);
/* Board type */
enum board_type {
diff --git a/src/soc/intel/skylake/romstage/Makefile.inc b/src/soc/intel/skylake/romstage/Makefile.inc
index 1b069b6..dff89ce 100644
--- a/src/soc/intel/skylake/romstage/Makefile.inc
+++ b/src/soc/intel/skylake/romstage/Makefile.inc
@@ -1,4 +1,3 @@
romstage-y += ../../../../cpu/intel/car/romstage.c
romstage-y += romstage.c
romstage-y += systemagent.c
-romstage-y += pch.c
diff --git a/src/soc/intel/skylake/romstage/pch.c b/src/soc/intel/skylake/romstage/pch.c
deleted file mode 100644
index c85bdd6..0000000
--- a/src/soc/intel/skylake/romstage/pch.c
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <intelblocks/smbus.h>
-#include <intelblocks/tco.h>
-#include <soc/romstage.h>
-
-void romstage_pch_init(void)
-{
- /* Program TCO_BASE_ADDRESS and TCO Timer Halt */
- tco_configure();
-
- /* Program SMBUS_BASE_ADDRESS and enable it */
- smbus_common_init();
-}
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index 99f444a..c709cf8 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -21,6 +21,7 @@
#include <soc/systemagent.h>
#include <string.h>
#include <security/vboot/vboot_common.h>
+#include <intelbasecode/romstage.h>
#include "../chip.h"
@@ -37,6 +38,8 @@
CHANNEL_PRESENT
};
+void romstage_cpu_init(void) {/*Stub function*/}
+
/* Save the DIMM information for SMBIOS table 17 */
static void save_dimm_info(void)
{
@@ -126,20 +129,10 @@
printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt);
}
-void mainboard_romstage_entry(void)
+void romstage_soc_post_mem_init(void)
{
- bool s3wake;
- struct chipset_power_state *ps;
-
- /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */
- systemagent_early_init();
- /* Program PCH init */
- romstage_pch_init();
- ps = pmc_get_power_state();
- s3wake = pmc_fill_power_state(ps) == ACPI_S3;
- fsp_memory_init(s3wake);
pmc_set_disb();
- if (!s3wake)
+ if (!romstage_is_s3wake())
save_dimm_info();
}
@@ -269,7 +262,7 @@
m_cfg->PrimaryDisplay = config->PrimaryDisplay;
}
-void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
+void romstage_soc_mem_init_params(FSPM_UPD *mupd, uint32_t version)
{
const struct soc_intel_skylake_config *config;
FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
@@ -303,6 +296,10 @@
soc_primary_gfx_config_params(m_cfg, config);
m_t_cfg->SkipExtGfxScan = config->SkipExtGfxScan;
+}
+
+void romstage_mb_mem_init_params(FSPM_UPD *mupd)
+{
mainboard_memory_init_params(mupd);
}
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