I'm not sure a root port without an attached endpoint should be able to enable ASPM, how can it know the device will be capable of it?

If you remove the generic device from 0:7.x in chipset.cb it also does not enable ASPM, so this is not restoring any previous behavior and uses the generic device to force the link to do things that I don't think it should be able to if no device is present.

In addition, PCI endpoints that exist on a root port at boot time are already handled properly so repeats things twice on root ports where there is actually a PCI endpoint attached.

 do_pci_scan_bridge for PCI: 00:1c.0
 PCI: pci_scan_bus for bus 2c
 PCI: 2c:00.0 [17a0/0000] ops
 GL9755: configure ASPM and LTR
 PCI: 2c:00.0 [17a0/9755] enabled
 GENERIC: 0.0 enabled
 Enabling Common Clock Configuration
 L1 Sub-State supported from root port 28
 L1 Sub-State Support = 0xf
 CommonModeRestoreTime = 0xff
 Power On Value = 0x1f, Power On Scale = 0x2
 ASPM: Enabled L1
 PCIe: Max_Payload_Size adjusted to 128
-scan_bus: bus PCI: 00:1c.0 finished in 0 msecs
+Enabling Common Clock Configuration
+L1 Sub-State supported from root port 28
+L1 Sub-State Support = 0xf
+CommonModeRestoreTime = 0xff
+Power On Value = 0x1f, Power On Scale = 0x2
+ASPM: Enabled L1
+PCIe: Max_Payload_Size adjusted to 128
+scan_bus: bus PCI: 00:1c.0 finished in 8 msecs

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