Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/23027 )
Change subject: mb/solidrun/solidpc: Do initial commit ......................................................................
Patch Set 12:
(2 comments)
https://review.coreboot.org/c/coreboot/+/23027/12/src/mainboard/solidrun/sol... File src/mainboard/solidrun/solidpc/Kconfig:
https://review.coreboot.org/c/coreboot/+/23027/12/src/mainboard/solidrun/sol... PS12, Line 6: ENABLE_BUILTIN_COM1
Not used on braswell (but should be implemented like on ~baytrail)
This is actually built-in serial port in the LPC, present on braswell and used on this board. The name is not misleading in any way. Can move the implementation out of mainboard directory as mentioned in other comment.
https://review.coreboot.org/c/coreboot/+/23027/12/src/mainboard/solidrun/sol... File src/mainboard/solidrun/solidpc/com_init.c:
https://review.coreboot.org/c/coreboot/+/23027/12/src/mainboard/solidrun/sol... PS12, Line 26: : uint32_t *pad_config_reg; : : /* Enable the UART hardware for COM1. */ : pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, 1); : : /* : * Set up the pads to select the UART function : * AD12 SW16(UART1_DATAIN/UART0_DATAIN) - Setting Mode 2 for UART0_RXD : * AD10 SW20(UART1_DATAOUT/UART0_DATAOUT) - Setting Mode 2 for UART0_TXD : */ : pad_config_reg = gpio_pad_config_reg(GP_SOUTHWEST, UART1_RXD_PAD); : write32(pad_config_reg, SET_PAD_MODE_SELECTION(PAD_CONFIG0_DEFAULT0, : M2)); : : pad_config_reg = gpio_pad_config_reg(GP_SOUTHWEST, UART1_TXD_PAD); : write32(pad_config_reg, SET_PAD_MODE_SELECTION(PAD_CONFIG0_DEFAULT0, : M2));
This should probably not be in the MB dir.
No braswell board in coreboot except SolidPC uses it, however I agree it can be moved out to soc/braswell