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26 comments:

• File src/soc/mediatek/mt8192/dramc_ana_init_config.c:

  • Patch Set #2, Line 1182: dq_pick = (tr->dq_semi_open == 1) ? 0 : (data_rate/2) ;

    space prohibited before semicolon

  • Patch Set #2, Line 1206: (ca_pick * 2 *(tr->ca_ckdiv4_en + 1))) ?

    need consistent spacing around '*' (ctx:WxV)

• File src/soc/mediatek/mt8192/dramc_pi_calibration_api.c:

  • Patch Set #2, Line 386: if (loop_cnt > early_break_cnt)

    Too many leading tabs - consider code refactoring

  • Patch Set #2, Line 2428: if ((vref_win_perbit[bit].last_pass !=

    Too many leading tabs - consider code refactoring

  • Patch Set #2, Line 2435: if (perbit_winsum > TX_PASS_WIN_CRITERIA)

    Too many leading tabs - consider code refactoring

• File src/soc/mediatek/mt8192/dramc_pi_main.c:

  • Patch Set #2, Line 201: SET32_BITFIELDS(&ch[chn].ao.shu_ac_time_05t, SHU_AC_TIME_05T_TRFC_05T, trfc_05t);

    line over 96 characters

  • Patch Set #2, Line 204: SET32_BITFIELDS(&ch[chn].ao.shu_ac_time_05t, SHU_AC_TIME_05T_TRFCPB_05T, trfrc_pb05t);

    line over 96 characters

• File src/soc/mediatek/mt8192/include/soc/pll.h:

  • Patch Set #2, Line 313: INFRACFG_AO_AXIMEM_BUS_DCM_REG0_MASK = ((0x1f << 12) | \

    Avoid unnecessary line continuations

  • Patch Set #2, Line 316: INFRACFG_AO_AXIMEM_BUS_DCM_REG0_ON = ((0x10 << 12) | \

    Avoid unnecessary line continuations

  • Patch Set #2, Line 319: INFRACFG_AO_INFRA_BUS_DCM_REG0_MASK = ((0x1 << 0) | \

    Avoid unnecessary line continuations

  • Patch Set #2, Line 328: INFRACFG_AO_INFRA_BUS_DCM_REG0_ON = ((0x1 << 0) | \

    Avoid unnecessary line continuations

  • Patch Set #2, Line 343: INFRACFG_AO_PERI_BUS_DCM_REG0_MASK = ((0x1 << 0) | \

    Avoid unnecessary line continuations

  • Patch Set #2, Line 352: INFRACFG_AO_PERI_BUS_DCM_REG0_ON = ((0x1 << 0) | \

    Avoid unnecessary line continuations

  • Patch Set #2, Line 361: INFRACFG_AO_PERI_MODULE_DCM_REG0_MASK = ((0x1 << 29) | \

    Avoid unnecessary line continuations

  • Patch Set #2, Line 363: INFRACFG_AO_PERI_MODULE_DCM_REG0_ON = ((0x1 << 29) | \

    Avoid unnecessary line continuations

• File src/soc/mediatek/mt8192/include/soc/rtc.h:

  • Patch Set #2, Line 101: RTC_GP_OSC32_CON = 2U << 13, /* Keep RG_EOSC_RSV[0] to low for lower leakage current hw design change */

    line over 96 characters

  • Patch Set #2, Line 106: OSC32CON_ANALOG_SETTING = RTC_GP_OSC32_CON | RTC_EOSC32_CHOP_EN | RTC_EOSC32_VCT_EN |\

    Avoid unnecessary line continuations

  • Patch Set #2, Line 107: RTC_GPS_CKOUT_EN | RTC_EMBCK_SEL_OPTION | RTC_EMB_K_EOSC32_MODE

    line over 96 characters

• File src/soc/mediatek/mt8192/pll.c:

  • Patch Set #2, Line 439: INFRACFG_AO_INFRA_CONN_BUS_DCM_REG0_MASK, INFRACFG_AO_INFRA_CONN_BUS_DCM_REG0_ON);

    line over 96 characters

  • Patch Set #2, Line 441: INFRACFG_AO_INFRA_CONN_BUS_DCM_REG1_MASK, INFRACFG_AO_INFRA_CONN_BUS_DCM_REG1_ON);

    line over 96 characters

• File src/soc/mediatek/mt8192/rtc.c:

  • Patch Set #2, Line 179: if (middle == left) {

    braces {} are not necessary for single statement blocks

  • Patch Set #2, Line 184: if (val >= RTC_FQMTR_LOW_BASE && val <= RTC_FQMTR_HIGH_BASE) {

    braces {} are not necessary for single statement blocks

  • Patch Set #2, Line 187: if (val > RTC_FQMTR_HIGH_BASE) {

    braces {} are not necessary for any arm of this statement

  • Patch Set #2, Line 190: else {

    else should follow close brace '}'

  • Patch Set #2, Line 296: rtc_write(RTC_BBPU, (bbpu | RTC_BBPU_KEY | RTC_BBPU_RESET_ALARM | RTC_BBPU_RESET_SPAR) & (~RTC_BBPU_SPAR_SW));

    line over 96 characters

  • Patch Set #2, Line 362: rtc_write(RTC_AL_YEA, (year | RTC_K_EOSC_RSV_0) & (~RTC_K_EOSC_RSV_1) & (~RTC_K_EOSC_RSV_2));

    line over 96 characters

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