2 comments:
PCI1 device been created based on TCSS_PCIE_SEGMENT selection
from MB Kconfig
I would like to know more about the motivation and reasoning behind this change.
To add support for multiple segment present in TGL SOC for iTBT
https://github.com/otcshare/CCG-TGL-Generic-SiC/blob/master/ClientOneSiliconPkg/IpBlock/Tcss/AcpiTables/SegSsdt/SegSsdt.asl#L67
Also, how was this tested?
ITBT root port should enumerated when multi seg function enable
File src/soc/intel/common/block/acpi/acpi/extrahostbridge.asl:
/* PCI Memory Region (TLUD - 0xdfffffff) */
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
NonCacheable, ReadWrite,
0x00000000, 0x00000000, 0xdfffffff, 0x00000000,
0xE0000000,,, PM01)
/* PCI Memory Region (TUUD - (TUUD + ABOVE_4G_MMIO_SIZE)) */
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
NonCacheable, ReadWrite,
0x00000000, 0x10000, 0x1ffff, 0x00000000,
0x10000,,, PM02)
These are exported by both the northbridge. […]
Refer to
https://github.com/otcshare/CCG-TGL-Generic-SiC/blob/master/ClientOneSiliconPkg/IpBlock/Tcss/AcpiTables/SegSsdt/ExtraHostBus.asl#L73
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