Arthur Heymans (arthur@aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15491
-gerrit
commit 233e9de0c9e0fc81cd0a03bd9fb42bf7ec09bc91 Author: Arthur Heymans arthur@aheymans.xyz Date: Sat Jun 18 21:08:58 2016 +0200
x4x: add non documented vram sizes
The Intel documtentation, "Intel ® 4 Series Chipset Family" mentions the possibility of 1, 4, 8 and 16M of preallocated memory for the IGD, but does not document this.
This allows to set those undocumented values.
Change-Id: I92beb8d78907d4514a5aaf69248dd607dcf227c0 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- src/northbridge/intel/x4x/ram_calc.c | 2 +- src/northbridge/intel/x4x/raminit_ddr2.c | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/ram_calc.c index 27562ea..5a6a767 100644 --- a/src/northbridge/intel/x4x/ram_calc.c +++ b/src/northbridge/intel/x4x/ram_calc.c @@ -28,7 +28,7 @@ /** Decodes used Graphics Mode Select (GMS) to kilobytes. */ u32 decode_igd_memory_size(const u32 gms) { - static const u16 ggc2uma[] = { 0, 0, 0, 0, 0, + static const u16 ggc2uma[] = { 0, 1, 4, 8, 16, 32, 48, 64, 128, 256, 96, 160, 224, 352 };
if (gms > ARRAY_SIZE(ggc2uma)) diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c index 5acb127..cc5624f 100644 --- a/src/northbridge/intel/x4x/raminit_ddr2.c +++ b/src/northbridge/intel/x4x/raminit_ddr2.c @@ -1626,7 +1626,8 @@ static void mmap_ddr2(struct sysinfo *s) u32 gfxsize, gttsize, tsegsize, mmiosize, tom, tolud, touud; u32 gfxbase, gttbase, tsegbase, reclaimbase, reclaimlimit; u16 ggc; - u16 ggc2uma[] = { 0, 0, 0, 0, 0, 32, 48, 64, 128, 256, 96, 160, 224, 352 }; + u16 ggc2uma[] = { 0, 1, 4, 8, 16, 32, 48, 64, 128, 256, 96, + 160, 224, 352 }; u8 ggc2gtt[] = { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4};
ggc = pci_read_config16(PCI_DEV(0,0,0), 0x52);