Patrick Georgi submitted this change.
soc/intel/common/cpu: Don't set any TCC settings if offset is 0
Many previous versions of this function would return early if tcc_offset
is 0. This adds that logic back in.
Change-Id: Ibc529520a4e74608cb5d20e5a6e8fc2c727c903c
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
---
M src/soc/intel/common/block/cpu/cpulib.c
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c
index 0ac8dda..e4ab664 100644
--- a/src/soc/intel/common/block/cpu/cpulib.c
+++ b/src/soc/intel/common/block/cpu/cpulib.c
@@ -260,15 +260,20 @@
const config_t *conf = config_of_soc();
msr_t msr;
+ if (!conf->tcc_offset)
+ return;
+
/* Set TCC activation offset */
msr = rdmsr(MSR_PLATFORM_INFO);
- if ((msr.lo & BIT(30)) && conf->tcc_offset) {
+ if ((msr.lo & BIT(30))) {
msr = rdmsr(MSR_TEMPERATURE_TARGET);
msr.lo &= ~(0xf << 24);
msr.lo |= (conf->tcc_offset & 0xf) << 24;
wrmsr(MSR_TEMPERATURE_TARGET, msr);
}
+
msr = rdmsr(MSR_TEMPERATURE_TARGET);
+
/* Time Window Tau Bits [6:0] */
msr.lo &= ~0x7f;
msr.lo |= 0xe6; /* setting 100ms thermal time window */
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