[coreboot-gerrit] Patch merged into coreboot/master: b1b9e4e exynos5420: Assign corect parent PLLs

the following patch was just integrated into master:
commit b1b9e4e583a451b97fbd379e2b1f8ecc16e12119
Author: David Hendricks 
Date:   Mon Aug 12 14:52:45 2013 -0700

exynos5420: Assign corect parent PLLs

Assign correct parent PLL's for the following clocks:
    ACLK_400_WCORE (MPLL->CPLL) (400 -> 333MHz)
    PCLK_200_FSYS (MPLL->DPLL) (200 -> 200MHz)
    MUX_ACLK_100_NOC_SEL (MPLL -> DPLL) (100 -> 100MHz)
    ACLK_266 (DPLL->MPLL) (300 -> 266MHz)
    ACLK_200_DISP1(MPLL->DPLL) (200 -> 200MHz)
    ACLK_400_MSCL(MPLL->CPLL) (400 -> 333MHz)
    ACLK_66 (MPLL->CPLL) (66.666 -> 66.6MHz)
    MUX_ACLK_400_DISP1_SEL (CPLL->DPLL) (666 -> 300MHz)
    MUX_MPHY_REFCLK (MPLL->OSC)
    MUX_UNIPRO (MPLL->OSC)
    MUX_MIPI1 (EPLL->OSC)
    MUX_DP1_EXT_VID (EPLL->OSC)
    MUX_FIMD1_OPT (EPLL->OSC)
    MUX_IPLL(IPLL->OSC)
    This also corrects the clock dividers for few of the clocks,
    as the clock parent changes affect the final frequency of the
    clocks.

This is ported from: https://gerrit.chromium.org/gerrit/#/c/62437/

Signed-off-by: David Hendricks

Change-Id: Ie833c01913d0961a6190446bd573511de8dee5f8
    Reviewed-on: https://gerrit.chromium.org/gerrit/65620
    Commit-Queue: Ronald G. Minnich 
    Reviewed-by: Ronald G. Minnich 
    Tested-by: Ronald G. Minnich

See http://review.coreboot.org/4469 for details.

-gerrit