Michał Żygowski submitted this change.
mb/pcengines/apu2: Switch to proper GPIO API
Use the abstractions <gpio.h> provides.
Change-Id: I348ba43a76287be5b24012ae3dfc28ed783da9c7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42521
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
---
M src/mainboard/pcengines/apu2/gpio_ftns.c
M src/mainboard/pcengines/apu2/gpio_ftns.h
M src/mainboard/pcengines/apu2/mainboard.c
M src/mainboard/pcengines/apu2/romstage.c
4 files changed, 45 insertions(+), 100 deletions(-)
diff --git a/src/mainboard/pcengines/apu2/gpio_ftns.c b/src/mainboard/pcengines/apu2/gpio_ftns.c
index c249c2d..28b9a74 100644
--- a/src/mainboard/pcengines/apu2/gpio_ftns.c
+++ b/src/mainboard/pcengines/apu2/gpio_ftns.c
@@ -1,68 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <stdint.h>
#include <amdblocks/acpimmio.h>
-#include <console/console.h>
-#include <device/mmio.h>
-#include <FchPlatform.h>
+#include <gpio.h>
#include "gpio_ftns.h"
-static u32 gpio_read_wrapper(u32 iomux_gpio)
-{
- u32 gpio = iomux_gpio << 2;
-
- if (gpio < 0x100)
- return gpio0_read32(gpio & 0xff);
- else if (gpio >= 0x100 && gpio < 0x200)
- return gpio1_read32(gpio & 0xff);
- else if (gpio >= 0x200 && gpio < 0x300)
- return gpio2_read32(gpio & 0xff);
-
- die("Invalid GPIO");
-}
-
-static void gpio_write_wrapper(u32 iomux_gpio, u32 setting)
-{
- u32 gpio = iomux_gpio << 2;
-
- if (gpio < 0x100)
- gpio0_write32(gpio & 0xff, setting);
- else if (gpio >= 0x100 && gpio < 0x200)
- gpio1_write32(gpio & 0xff, setting);
- else if (gpio >= 0x200 && gpio < 0x300)
- gpio2_write32(gpio & 0xff, setting);
-}
-
-void configure_gpio(u32 gpio, u8 iomux_ftn, u32 setting)
-{
- u32 bdata;
-
- bdata = gpio_read_wrapper(gpio);
- /* out the data value to prevent glitches */
- bdata |= (setting & GPIO_OUTPUT_ENABLE);
- gpio_write_wrapper(gpio, bdata);
-
- /* set direction and data value */
- bdata |= (setting & (GPIO_OUTPUT_ENABLE | GPIO_OUTPUT_VALUE
- | GPIO_PULL_UP_ENABLE | GPIO_PULL_DOWN_ENABLE));
- gpio_write_wrapper(gpio, bdata);
-
- iomux_write8(gpio, iomux_ftn & 0x3);
-}
-
-u8 read_gpio(u32 gpio)
-{
- return (gpio_read_wrapper(gpio) & GPIO_PIN_STS) ? 1 : 0;
-}
-
-void write_gpio(u32 gpio, u8 value)
-{
- u32 status = gpio_read_wrapper(gpio);
- status &= ~GPIO_OUTPUT_VALUE;
- status |= (value > 0) ? GPIO_OUTPUT_VALUE : 0;
- gpio_write_wrapper(gpio, status);
-}
-
int get_spd_offset(void)
{
u8 index = 0;
@@ -70,10 +11,10 @@
* One SPD file contains all 4 options, determine which index to
* read here, then call into the standard routines.
*/
- if (gpio1_read8(0x02) & BIT0)
- index |= BIT0;
- if (gpio1_read8(0x06) & BIT0)
- index |= BIT1;
+ if (gpio_get(GPIO_49))
+ index |= 1 << 0;
+ if (gpio_get(GPIO_50))
+ index |= 1 << 1;
return index;
}
diff --git a/src/mainboard/pcengines/apu2/gpio_ftns.h b/src/mainboard/pcengines/apu2/gpio_ftns.h
index d1e76de..95c744f 100644
--- a/src/mainboard/pcengines/apu2/gpio_ftns.h
+++ b/src/mainboard/pcengines/apu2/gpio_ftns.h
@@ -3,9 +3,6 @@
#ifndef GPIO_FTNS_H
#define GPIO_FTNS_H
-void configure_gpio(u32 gpio, u8 iomux_ftn, u32 setting);
-u8 read_gpio(u32 gpio);
-void write_gpio(u32 gpio, u8 value);
int get_spd_offset(void);
//
@@ -28,10 +25,4 @@
#define GPIO_68 0x48 // PE4_WDIS (SIMSWAP1 on APU5)
#define GPIO_71 0x4D // PROCHOT
-#define GPIO_OUTPUT_ENABLE BIT23
-#define GPIO_OUTPUT_VALUE BIT22
-#define GPIO_PULL_DOWN_ENABLE BIT21
-#define GPIO_PULL_UP_ENABLE BIT20
-#define GPIO_PIN_STS BIT16
-
#endif /* GPIO_FTNS_H */
diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c
index 40941db..bad1a57 100644
--- a/src/mainboard/pcengines/apu2/mainboard.c
+++ b/src/mainboard/pcengines/apu2/mainboard.c
@@ -6,6 +6,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci_def.h>
+#include <gpio.h>
#include <southbridge/amd/pi/hudson/hudson.h>
#include <southbridge/amd/pi/hudson/pci_devs.h>
#include <southbridge/amd/pi/hudson/amd_pci_int_defs.h>
@@ -265,8 +266,8 @@
//
// Turn off LED 2 and LED 3
//
- write_gpio(GPIO_58, 1);
- write_gpio(GPIO_59, 1);
+ gpio_set(GPIO_58, 1);
+ gpio_set(GPIO_59, 1);
}
/*
diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c
index 0fc472f..e0a63f0 100644
--- a/src/mainboard/pcengines/apu2/romstage.c
+++ b/src/mainboard/pcengines/apu2/romstage.c
@@ -2,9 +2,10 @@
#include <stdint.h>
#include <amdblocks/acpimmio.h>
+#include <console/console.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
-#include <console/console.h>
+#include <gpio.h>
#include <northbridge/amd/agesa/state_machine.h>
#include "gpio_ftns.h"
@@ -28,52 +29,63 @@
pm_write8(0xea, 1);
}
+static void pin_input(gpio_t gpio, u8 iomux_ftn)
+{
+ iomux_write8(gpio, iomux_ftn);
+ gpio_input(gpio);
+}
+
+static void pin_low(gpio_t gpio, u8 iomux_ftn)
+{
+ iomux_write8(gpio, iomux_ftn);
+ gpio_output(gpio, 0);
+}
+
+static void pin_high(gpio_t gpio, u8 iomux_ftn)
+{
+ iomux_write8(gpio, iomux_ftn);
+ gpio_output(gpio, 1);
+}
+
static void early_lpc_init(void)
{
- u32 setting = 0x0;
-
//
- // Configure output disabled, value low, pull up/down disabled
+ // Configure output disabled, pull up/down disabled
//
- if (CONFIG(BOARD_PCENGINES_APU5)) {
- configure_gpio(GPIO_22, Function0, setting);
- }
+ if (CONFIG(BOARD_PCENGINES_APU5))
+ pin_input(GPIO_22, Function0);
if (CONFIG(BOARD_PCENGINES_APU2) ||
CONFIG(BOARD_PCENGINES_APU3) ||
CONFIG(BOARD_PCENGINES_APU4)) {
- configure_gpio(GPIO_32, Function0, setting);
+ pin_input(GPIO_32, Function0);
}
- configure_gpio(GPIO_49, Function2, setting);
- configure_gpio(GPIO_50, Function2, setting);
- configure_gpio(GPIO_71, Function0, setting);
+ pin_input(GPIO_49, Function2);
+ pin_input(GPIO_50, Function2);
+ pin_input(GPIO_71, Function0);
//
// Configure output enabled, value low, pull up/down disabled
//
- setting = GPIO_OUTPUT_ENABLE;
if (CONFIG(BOARD_PCENGINES_APU3) ||
CONFIG(BOARD_PCENGINES_APU4)) {
- configure_gpio(GPIO_33, Function0, setting);
+ pin_low(GPIO_33, Function0);
}
-
- configure_gpio(GPIO_57, Function1, setting);
- configure_gpio(GPIO_58, Function1, setting);
- configure_gpio(GPIO_59, Function3, setting);
+ pin_low(GPIO_57, Function1);
+ pin_low(GPIO_58, Function1);
+ pin_low(GPIO_59, Function3);
//
// Configure output enabled, value high, pull up/down disabled
//
- setting = GPIO_OUTPUT_ENABLE | GPIO_OUTPUT_VALUE;
-
if (CONFIG(BOARD_PCENGINES_APU5)) {
- configure_gpio(GPIO_32, Function0, setting);
- configure_gpio(GPIO_33, Function0, setting);
+ pin_high(GPIO_32, Function0);
+ pin_high(GPIO_33, Function0);
}
- configure_gpio(GPIO_51, Function2, setting);
- configure_gpio(GPIO_55, Function3, setting);
- configure_gpio(GPIO_64, Function2, setting);
- configure_gpio(GPIO_68, Function0, setting);
+ pin_high(GPIO_51, Function2);
+ pin_high(GPIO_55, Function3);
+ pin_high(GPIO_64, Function2);
+ pin_high(GPIO_68, Function0);
}
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