Krishna P Bhat D uploaded patch set #2 to this change.

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soc/intel/cannonlake: Clear SUS_PWR_FLR status bit

The prev_sleep_state value was showing 5 even after warm reboot, once the
SUS_PWR_FLR bit is being set. This bit was not being cleared.
Hence clearing the SUS_PWR_FLR bit.

BUG=b:128482282
BRANCH=None
TEST=In cbmem logs, check for value of “prev_sleep_state” using command
cbmem –c | grep “prev_sleep_state”

For cold reboot, "prev_sleep_state 5"
For warm reboot, "prev_sleep_state 0"

Change-Id: If9863d52ed3c61b6a160df53f023b0787eaaed68
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
---
M src/soc/intel/cannonlake/include/soc/pm.h
M src/soc/intel/cannonlake/pmc.c
M src/soc/intel/cannonlake/pmutil.c
3 files changed, 22 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/31902/2

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