HACK: Random SPM debugging code

Change-Id: I5880a91628e6999094257c49d1a4f0348fc69eeb
---
M src/soc/mediatek/mt8192/spm.c
1 file changed, 46 insertions(+), 3 deletions(-)


git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/47359/1

diff --git a/src/soc/mediatek/mt8192/spm.c b/src/soc/mediatek/mt8192/spm.c
index e263fc3..cf8b10e 100644
--- a/src/soc/mediatek/mt8192/spm.c
+++ b/src/soc/mediatek/mt8192/spm.c
@@ -493,6 +493,9 @@
 	u32 dmem_start;
 	u32 con0;
 
+	printk(BIOS_INFO, "SPM firmware @%08lx (Pmem:%08x/Total:%08x).\n",
+		(long)(pcm->buf), pcm->desc.pmem_words, pcm->desc.total_words);
+
 	ptr = (uintptr_t) pcm->buf + 0x40000000;
 	pmem_words = pcm->desc.pmem_words;
 	total_words = pcm->desc.total_words;
@@ -517,7 +520,23 @@
 		write32(&mtk_spm->md32pcm_dma0_wpto, dmem_start);
 		write32(&mtk_spm->md32pcm_dma0_count, total_words);
 		write32(&mtk_spm->md32pcm_dma0_con, MD32PCM_DMA0_CON_VAL);
+		write32(&mtk_spm->md32pcm_dma0_start, 0);
 		write32(&mtk_spm->md32pcm_dma0_start, MD32PCM_DMA0_START_VAL);
+
+		{
+			u32 rlct[32]; u32 pc[32]; int i;
+			for (i = 0; i < ARRAY_SIZE(rlct); i++) {
+				pc[i] = read32(&mtk_spm->md32pcm_pc);
+				rlct[i] = read32(&mtk_spm->md32pcm_dma0_rlct);
+				udelay(1);
+			}
+
+			printk(BIOS_INFO, "spm md32pcm_dma0_rlct @%08lx\n", (long)&mtk_spm->md32pcm_dma0_rlct);
+			for (i = 0; i < ARRAY_SIZE(rlct); i++) {
+				printk(BIOS_INFO, "spm rlct[%d] = 0x%x\n", i, rlct[i]);
+				printk(BIOS_INFO, "spm pc[%d] = 0x%x\n", i, pc[i]);
+			}
+		}
 	} else {
 		write32(&mtk_spm->pcm_con1, read32(&mtk_spm->pcm_con1) |
 			SPM_REGWR_CFG_KEY | RG_IM_SLAVE_LSB);
@@ -526,6 +545,7 @@
 	/* kick IM to fetch (only toggle IM_KICK) */
 	con0 = read32(&mtk_spm->pcm_con0);
 	write32(&mtk_spm->pcm_con0, con0 | SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB);
+	printk(BIOS_INFO, "SPM con0 0x%08x/0x%08x\n", con0, con0 | SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB);
 }
 
 #define SPM_DEBUG_DUMP 1
@@ -721,9 +741,12 @@
 	write32(&mtk_spm->spm_sw_rsv_8, pwrctrl->pcm_flags1);
 }
 
+static u32 pc[4096];
+
 static void spm_kick_pcm_to_run(struct pwr_ctrl *pwrctrl)
 {
 	u32 con0, rstn;
+	int i, cnt;
 
 	/* Waiting for loading SPMFW done*/
 	while (read32(&mtk_spm->md32pcm_dma0_rlct) != 0x0)
@@ -746,14 +769,24 @@
 	write32(&mtk_spm->md32pcm_cfgreg_sw_rstn,
 		rstn | MD32PCM_CFGREG_SW_RSTN_RESET);
 
-	/* Waiting for SPM init done */
-	udelay(SPM_INIT_DONE_US);
+	for (cnt = 0; cnt < ARRAY_SIZE(pc); cnt++) {
+		pc[cnt] = read32(&mtk_spm->md32pcm_pc);
+		if (pc[cnt] == 0x3f4)
+			break;
+		/* Waiting for SPM init done */
+		//udelay(SPM_INIT_DONE_US/ARRAY_SIZE(pc));
+	}
+
+	printk(BIOS_INFO, "spm pc @%08lx (%d loops)\n", (long)&mtk_spm->md32pcm_pc, cnt);
+	for (i = 0; i < cnt; i++)
+		printk(BIOS_INFO, "spm pc[%d] = 0x%x\n", i, pc[i]);
 }
 
-int spm_init(void)
+static inline int spm_init_lon(void)
 {
 	struct dyna_load_pcm pcm;
 	struct stopwatch sw;
+	int i;
 
 	stopwatch_init(&sw);
 
@@ -780,5 +813,15 @@
 	       __func__, stopwatch_duration_msecs(&sw),
 	       read32(&mtk_spm->md32pcm_pc));
 
+	for (i = 0; i < sizeof(*mtk_spm)/4; i++) {
+		u32* p = (u32 *)mtk_spm;
+		printk(BIOS_INFO, "SPM: %08lx=%08x\n", (long)&p[i], read32(&p[i]));
+	}
+
 	return 0;
 }
+
+int spm_init(void) {
+	/* Shorten __func__ in function above */
+	return spm_init_lon();
+}

