Attention is currently required from: Werner Zeh, Jan Samek.
Jan Samek uploaded patch set #4 to the change originally created by Angel Pons.
mb/siemens/mc_apl*: Enable early PCI bridge before FSP-M
Apollo Lake seems to start with PCIe root ports unusable/uninitialized
before FspMemoryInit() is called and FSP-M properly initializes these
root ports.
However, we need the root ports accessible before FspMemoryInit() in
certain cases, such as emitting POST codes through a PCIe device.
For the initialization to happen properly, certain register writes
specified in Apollo Lake IAFW BIOS spec, vol. 2 (#559811), chapter
3.3.1 have to be done.
BUG=none
TEST=Boot on siemens/mc_apl2 with NC_FPGA_POST_CODE enabled and check
that the POST codes are emitted before FspMemoryInit().
Change-Id: If782bfdd5f499dd47c085a0a16b4b15832bc040e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Signed-off-by: Jan Samek <jan.samek@siemens.com>
---
M src/mainboard/siemens/mc_apl1/bootblock.c
1 file changed, 49 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/68223/4
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