awokd@danwin1210.me uploaded patch set #3 to this change.

View Change

vc/amd/agesa: Fix out of bounds read

ByteLane is used unitialized from prior for statement,
creating a potential out-of-bound read of RxOrig[MaxByteLanes].
PassTestRxEnDly[MaxByteLanes] never appears as rvalue; all for
loops have ByteLane < MaxByteLanes exit condition.
If the intent here was to preload the PassTestRxEnDly array
with RxOrig's contents, there is nothing following with the
OutOfRange[ByteLane]==TRUE condition that uses it.

Change-Id: Icd18a146aba6b6120d37518d8c40c7efbc05afa3
Signed-off-by: Joe Moore <awokd@danwin1210.me>
Found-by: Coverity CID 1241804
---
M src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mtthrcSeedTrain.c
M src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mtthrcSeedTrain.c
M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c
3 files changed, 0 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/36192/3

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