Anonymous Coward #1001664 has uploaded this change for review. ( https://review.coreboot.org/20124
Change subject: riscv: Update register address ......................................................................
riscv: Update register address
I triggered a bug, when I try to debug riscv code by spike. This bug is caused by an instruction exception[csrwi 0x320,7]. This is operate for mcounteren. This address is error. 0x306 is right. scounteren is not need to be set, because S-mode code controls it.
Change-Id: I0a970940c191dae9543dcadb19480efcf5ea6956 Signed-off-by: wxjstz wxjstz@126.com --- M src/arch/riscv/virtual_memory.c M src/mainboard/emulation/spike-riscv/uart.c 2 files changed, 3 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/20124/1
diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c index 2c440d2..1fff1d1 100644 --- a/src/arch/riscv/virtual_memory.c +++ b/src/arch/riscv/virtual_memory.c @@ -311,11 +311,10 @@ set_csr(medeleg, delegate);
// Enable all user/supervisor-mode counters using - // v1.9.1 register addresses. + // v1.10 register addresses. // They moved from the earlier spec. // Until we trust our toolchain use the hardcoded constants. // These were in flux and people who get the older toolchain // will have difficult-to-debug failures. - write_csr(/*mucounteren*/0x320, 7); - write_csr(/*mscounteren*/0x321, 7); + write_csr(/*mcounteren*/0x306, 7); } diff --git a/src/mainboard/emulation/spike-riscv/uart.c b/src/mainboard/emulation/spike-riscv/uart.c index 57647fe..26ab630 100644 --- a/src/mainboard/emulation/spike-riscv/uart.c +++ b/src/mainboard/emulation/spike-riscv/uart.c @@ -20,5 +20,5 @@
uintptr_t uart_platform_base(int idx) { - return (uintptr_t) 0x40001000; + return (uintptr_t) 0x02100000; }