Nick Vaccaro has uploaded this change for review.
mb/google/volteer: add volteer mainboard initial support
BUG=b:142961277
BRANCH=master
TEST="emerge-volteer coreboot" compiles successfully.
Change-Id: I03a13f3df4e819ab9cf63ad69867c807d2a1b651
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
---
A src/mainboard/google/volteer/Kconfig
A src/mainboard/google/volteer/Kconfig.name
A src/mainboard/google/volteer/Makefile.inc
A src/mainboard/google/volteer/acpi/mipi_camera.asl
A src/mainboard/google/volteer/acpi_tables.c
A src/mainboard/google/volteer/board_info.txt
A src/mainboard/google/volteer/bootblock.c
A src/mainboard/google/volteer/chromeos.c
A src/mainboard/google/volteer/chromeos.fmd
A src/mainboard/google/volteer/dsdt.asl
A src/mainboard/google/volteer/ec.c
A src/mainboard/google/volteer/mainboard.c
A src/mainboard/google/volteer/smihandler.c
A src/mainboard/google/volteer/spd/Makefile.inc
A src/mainboard/google/volteer/spd/samsung-K4U6E3S4AA-MGCL.spd.hex
A src/mainboard/google/volteer/variants/baseboard/Makefile.inc
A src/mainboard/google/volteer/variants/baseboard/devicetree.cb
A src/mainboard/google/volteer/variants/baseboard/gpio.c
A src/mainboard/google/volteer/variants/baseboard/include/baseboard/ec.h
A src/mainboard/google/volteer/variants/baseboard/include/baseboard/gpio.h
A src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h
A src/mainboard/google/volteer/variants/volteer/Makefile.inc
A src/mainboard/google/volteer/variants/volteer/include/variant/acpi/dptf.asl
A src/mainboard/google/volteer/variants/volteer/include/variant/ec.h
A src/mainboard/google/volteer/variants/volteer/include/variant/gpio.h
25 files changed, 2,204 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/38620/1
diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig
new file mode 100644
index 0000000..572a100
--- /dev/null
+++ b/src/mainboard/google/volteer/Kconfig
@@ -0,0 +1,71 @@
+config BOARD_GOOGLE_BASEBOARD_VOLTEER
+ def_bool n
+ select BOARD_ROMSIZE_KB_32768
+ select DRIVERS_GENERIC_MAX98357A
+ select DRIVERS_I2C_GENERIC
+ select DRIVERS_SPI_ACPI
+ select EC_GOOGLE_CHROMEEC
+ select EC_GOOGLE_CHROMEEC_BOARDID
+ select EC_GOOGLE_CHROMEEC_LPC
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select INTEL_LPSS_UART_FOR_CONSOLE
+ select MAINBOARD_HAS_CHROMEOS
+ select MAINBOARD_HAS_SPI_TPM_CR50
+ select MAINBOARD_HAS_TPM2
+ select SOC_INTEL_TIGERLAKE
+
+if BOARD_GOOGLE_BASEBOARD_VOLTEER
+
+config CHROMEOS
+ bool
+ default y
+ select EC_GOOGLE_CHROMEEC_SWITCHES
+ select GBB_FLAG_FORCE_DEV_SWITCH_ON
+ select GBB_FLAG_FORCE_DEV_BOOT_USB
+ select GBB_FLAG_FORCE_DEV_BOOT_LEGACY
+ select GBB_FLAG_FORCE_MANUAL_RECOVERY
+ select HAS_RECOVERY_MRC_CACHE
+ select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
+ select VBOOT_LID_SWITCH
+
+config DIMM_SPD_SIZE
+ int
+ default 512
+
+config DEVICETREE
+ string
+ default "variants/baseboard/devicetree.cb"
+
+config OVERRIDE_DEVICETREE
+ string
+ default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" if !BOARD_GOOGLE_VOLTEER
+
+config DRIVER_TPM_SPI_BUS
+ default 0x1
+
+config MAINBOARD_DIR
+ string
+ default "google/volteer"
+
+config MAINBOARD_FAMILY
+ string
+ default "Google_Volteer" if BOARD_GOOGLE_VOLTEER
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Volteer" if BOARD_GOOGLE_VOLTEER
+
+config MAX_CPUS
+ int
+ default 8
+
+config TPM_TIS_ACPI_INTERRUPT
+ int
+ default 21 # GPE0_DW0_21 (GPP_C21)
+
+config VARIANT_DIR
+ string
+ default "volteer" if BOARD_GOOGLE_VOLTEER
+
+endif # BOARD_GOOGLE_BASEBOARD_VOLTEER
diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name
new file mode 100644
index 0000000..a3fac9c
--- /dev/null
+++ b/src/mainboard/google/volteer/Kconfig.name
@@ -0,0 +1,5 @@
+comment "Volteer"
+
+config BOARD_GOOGLE_VOLTEER
+ bool "-> Volteer"
+ select BOARD_GOOGLE_BASEBOARD_VOLTEER
diff --git a/src/mainboard/google/volteer/Makefile.inc b/src/mainboard/google/volteer/Makefile.inc
new file mode 100644
index 0000000..34bb41a
--- /dev/null
+++ b/src/mainboard/google/volteer/Makefile.inc
@@ -0,0 +1,35 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2019 Google LLC
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+bootblock-y += bootblock.c
+
+romstage-$(CONFIG_CHROMEOS) += chromeos.c
+
+ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-y += ec.c
+ramstage-y += mainboard.c
+
+smm-y += smihandler.c
+
+verstage-$(CONFIG_CHROMEOS) += chromeos.c
+
+subdirs-y += variants/baseboard
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
+
+VARIANT_DIR:=$(call strip_quotes,$(CONFIG_VARIANT_DIR))
+subdirs-y += variants/$(VARIANT_DIR)
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
+
+subdirs-y += spd
diff --git a/src/mainboard/google/volteer/acpi/mipi_camera.asl b/src/mainboard/google/volteer/acpi/mipi_camera.asl
new file mode 100644
index 0000000..e1ecc3a
--- /dev/null
+++ b/src/mainboard/google/volteer/acpi/mipi_camera.asl
@@ -0,0 +1,530 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Scope (\_SB.PCI0)
+{
+ Device (IPU0)
+ {
+ Name (_ADR, 0x00050000)
+ Name (_DDN, "Camera and Imaging Subsystem")
+ }
+}
+
+Scope (\_SB.PCI0.IPU0)
+{
+ Name (_DSD, Package (0x02)
+ {
+ ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
+ Package (0x02)
+ {
+ Package (0x02)
+ {
+ "port0",
+ "PRT0"
+ },
+
+ Package (0x02)
+ {
+ "port1",
+ "PRT1"
+ }
+ }
+ })
+
+ Name (PRT0, Package (0x04)
+ {
+ ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package (0x01)
+ {
+ Package (0x02)
+ {
+ "port",
+ 5
+ }
+ },
+
+ ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
+ Package (0x01)
+ {
+ Package (0x02)
+ {
+ "endpoint0",
+ "EP00"
+ }
+ }
+ })
+
+ Name (PRT1, Package (0x04)
+ {
+ ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package (0x01)
+ {
+ Package (0x02)
+ {
+ "port",
+ 1
+ }
+ },
+
+ ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
+ Package (0x01)
+ {
+ Package (0x02)
+ {
+ "endpoint0",
+ "EP10"
+ }
+ }
+ })
+}
+
+Scope (_SB.PCI0.IPU0)
+{
+ Name (EP00, Package (0x02)
+ {
+ ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package (0x04)
+ {
+ Package (0x02)
+ {
+ "endpoint",
+ Zero
+ },
+
+ Package (0x02)
+ {
+ "clock-lanes",
+ Zero
+ },
+
+ Package (0x02)
+ {
+ "data-lanes",
+ Package (0x04)
+ {
+ One,
+ 0x02,
+ 0x03,
+ 0x04
+ }
+ },
+
+ Package (0x02)
+ {
+ "remote-endpoint",
+ Package (0x03)
+ {
+ ^I2C3.CAM0,
+ Zero,
+ Zero
+ }
+ }
+ }
+ })
+ Name (EP10, Package (0x02)
+ {
+ ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package (0x04)
+ {
+ Package (0x02)
+ {
+ "endpoint",
+ Zero
+ },
+
+ Package (0x02)
+ {
+ "clock-lanes",
+ Zero
+ },
+
+ Package (0x02)
+ {
+ "data-lanes",
+ Package (0x04)
+ {
+ One,
+ 0x02
+ }
+ },
+
+ Package (0x02)
+ {
+ "remote-endpoint",
+ Package (0x03)
+ {
+ ^I2C2.CAM1,
+ Zero,
+ Zero
+ }
+ }
+ }
+ })
+}
+
+Scope (\_SB.PCI0.I2C3)
+{
+ PowerResource (RCPR, 0x00, 0x0000)
+ {
+ Name (STA, Zero)
+ Method (_ON, 0, Serialized)
+ {
+ If ((STA == Zero))
+ {
+ /* Enable CLK3:19.2MHz */
+ MCCT(3,1,1)
+ /* Pull PWREN(GPIO H20) high */
+ STXS(GPP_H20)
+ Sleep(5)
+ /* Pull RST(GPIO D4) low */
+ CTXS(GPP_D4)
+ Sleep(5)
+ /* Pull RST high */
+ STXS(GPP_D4)
+ Sleep(5)
+ Store(1,STA)
+ }
+ }
+
+ Method (_OFF, 0, Serialized)
+ {
+ If ((STA == One))
+ {
+ /* Pull RST low */
+ CTXS(GPP_D4)
+ /* Pull PWREN low */
+ CTXS(GPP_H20)
+ /* Disable CLK3 */
+ MCCT(3,0,1)
+ Store(0,STA)
+ }
+ }
+
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (STA)
+ }
+ }
+
+ Device (CAM0)
+ {
+ Name (_HID, "OVTI8856")
+ Name (_UID, Zero)
+ Name (_DDN, "Ov 8856 Camera")
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0F)
+ }
+
+ Name (_CRS, ResourceTemplate ()
+ {
+ I2cSerialBus (0x0010, ControllerInitiated, 0x00061A80,
+ AddressingMode7Bit, "\\_SB.PCI0.I2C3",
+ 0x00, ResourceConsumer, ,
+ )
+ })
+
+ Name (_PR0, Package (0x01)
+ {
+ RCPR
+ })
+
+ Name (_PR3, Package (0x01)
+ {
+ RCPR
+ })
+
+ Name (_DSD, Package (0x04)
+ {
+ ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
+ Package (0x01)
+ {
+ Package (0x02)
+ {
+ "port0",
+ "PRT0"
+ }
+ },
+
+ ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package (0x02)
+ {
+ Package (0x02)
+ {
+ "clock-frequency",
+ 0x0124F800
+ },
+ Package (0x02)
+ {
+ "lens-focus",
+ Package (0x01)
+ {
+ VCM0
+ }
+ }
+ }
+ })
+
+ Name (PRT0, Package (0x04)
+ {
+ ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package (0x01)
+ {
+ Package (0x02)
+ {
+ "port",
+ Zero
+ }
+ },
+
+ ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
+ Package (0x01)
+ {
+ Package (0x02)
+ {
+ "endpoint0",
+ "EP00"
+ }
+ }
+ })
+
+ Name (EP00, Package (0x02)
+ {
+ ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package (0x03)
+ {
+ Package (0x02)
+ {
+ "endpoint",
+ Zero
+ },
+
+ Package (0x02)
+ {
+ "link-frequencies",
+ Package (0x01)
+ {
+ 0x325AA000
+ }
+ },
+ Package (0x02)
+ {
+ "remote-endpoint",
+ Package (0x03)
+ {
+ IPU0,
+ Zero,
+ Zero
+ }
+ }
+ }
+ })
+ }
+
+ Device (VCM0)
+ {
+ Name (_HID, "PRP0001")
+ Name (_UID, 0x03)
+ Name (_DDN, "DW9714 VCM")
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0F)
+ }
+
+ Name (_CRS, ResourceTemplate ()
+ {
+ I2cSerialBus (0x000C, ControllerInitiated, 0x00061A80,
+ AddressingMode7Bit, "\\_SB.PCI0.I2C3",
+ 0x00, ResourceConsumer, ,
+ )
+ })
+ Name (_DEP, Package (0x01)
+ {
+ CAM0
+ })
+ Name (_PR0, Package (0x01)
+ {
+ RCPR
+ })
+ Name (_PR3, Package (0x01)
+ {
+ RCPR
+ })
+ Name (_DSD, Package (0x02)
+ {
+ ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package (0x01)
+ {
+ Package (0x02)
+ {
+ "compatible",
+ "dongwoon,dw9714"
+ }
+ }
+ })
+ }
+}
+
+Scope (\_SB.PCI0.I2C2)
+{
+ PowerResource (FCPR, 0x00, 0x0000)
+ {
+ Name (STA, Zero)
+ Method (_ON, 0, Serialized)
+ {
+ If ((STA == Zero))
+ {
+ /* Enable CLK2 : 19.2MHz */
+ MCCT(2,1,1)
+ /* Pull PWREN(GPIO H20) high */
+ STXS(GPP_H20)
+ Sleep(5)
+ /* Pull RST(GPIO D4) low */
+ CTXS(GPP_D4)
+ Sleep(5)
+ /* Pull RST high */
+ STXS(GPP_D4)
+ Sleep(5)
+ Store(1,STA)
+ }
+ }
+
+ Method (_OFF, 0, Serialized)
+ {
+ If ((STA == One))
+ {
+ /* Pull RST low */
+ CTXS(GPP_D4)
+ /* Pull PWREN low */
+ CTXS(GPP_H20)
+ /* Disable CLK2 */
+ MCCT(2,0,1)
+ Store(0,STA)
+ }
+ }
+
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (STA)
+ }
+ }
+
+ Device (CAM1)
+ {
+ Name (_HID, "OVTI2740")
+ Name (_UID, Zero)
+ Name (_DDN, "Ov 2740 Camera")
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0F)
+ }
+
+ Name (_CRS, ResourceTemplate ()
+ {
+ I2cSerialBus (0x0010, ControllerInitiated, 0x00061A80,
+ AddressingMode7Bit, "\\_SB.PCI0.I2C0",
+ 0x00, ResourceConsumer, ,
+ )
+ })
+
+ Name (_PR0, Package (0x01)
+ {
+ FCPR
+ })
+
+ Name (_PR3, Package (0x01)
+ {
+ FCPR
+ })
+
+ Name (_DSD, Package (0x04)
+ {
+ ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
+ Package (0x01)
+ {
+ Package (0x02)
+ {
+ "port0",
+ "PRT0"
+ }
+ },
+
+ ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package (0x01)
+ {
+ Package (0x02)
+ {
+ "clock-frequency",
+ 0x0124F800
+ }
+ }
+ })
+
+ Name (PRT0, Package (0x04)
+ {
+ ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package (0x01)
+ {
+ Package (0x02)
+ {
+ "port",
+ Zero
+ }
+ },
+
+ ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
+ Package (0x01)
+ {
+ Package (0x02)
+ {
+ "endpoint0",
+ "EP00"
+ }
+ }
+ })
+
+ Name (EP00, Package (0x02)
+ {
+ ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package (0x03)
+ {
+ Package (0x02)
+ {
+ "endpoint",
+ Zero
+ },
+
+ Package (0x02)
+ {
+ "link-frequencies",
+ Package (0x01)
+ {
+ 0x325AA000
+ }
+ },
+ Package (0x02)
+ {
+ "remote-endpoint",
+ Package (0x03)
+ {
+ IPU0,
+ One,
+ Zero
+ }
+ }
+ }
+ })
+ }
+}
diff --git a/src/mainboard/google/volteer/acpi_tables.c b/src/mainboard/google/volteer/acpi_tables.c
new file mode 100644
index 0000000..3b44754
--- /dev/null
+++ b/src/mainboard/google/volteer/acpi_tables.c
@@ -0,0 +1 @@
+/* Nothing here */
diff --git a/src/mainboard/google/volteer/board_info.txt b/src/mainboard/google/volteer/board_info.txt
new file mode 100644
index 0000000..c41a04b
--- /dev/null
+++ b/src/mainboard/google/volteer/board_info.txt
@@ -0,0 +1,6 @@
+Vendor name: Google
+Board name: Volteer Tigerlake Reference Board
+Category: laptop
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/google/volteer/bootblock.c b/src/mainboard/google/volteer/bootblock.c
new file mode 100644
index 0000000..1127d2e
--- /dev/null
+++ b/src/mainboard/google/volteer/bootblock.c
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/variants.h>
+#include <bootblock_common.h>
+
+void bootblock_mainboard_init(void)
+{
+ const struct pad_config *pads;
+ size_t num;
+
+ pads = variant_early_gpio_table(&num);
+ gpio_configure_pads(pads, num);
+}
diff --git a/src/mainboard/google/volteer/chromeos.c b/src/mainboard/google/volteer/chromeos.c
new file mode 100644
index 0000000..6cda926
--- /dev/null
+++ b/src/mainboard/google/volteer/chromeos.c
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/variants.h>
+#include <boot/coreboot_tables.h>
+#include <gpio.h>
+#include <variant/gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+ struct lb_gpio chromeos_gpios[] = {
+ {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"},
+ {-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
+ {-1, ACTIVE_HIGH, 0, "power"},
+ {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
+ {GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW),
+ "EC in RW"},
+ };
+ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
+}
+
+int get_write_protect_state(void)
+{
+ /* Read PCH_WP GPIO. */
+ return gpio_get(GPIO_PCH_WP);
+}
+
+void mainboard_chromeos_acpi_generate(void)
+{
+ const struct cros_gpio *gpios;
+ size_t num;
+
+ gpios = variant_cros_gpios(&num);
+ chromeos_acpi_gpio_generate(gpios, num);
+}
diff --git a/src/mainboard/google/volteer/chromeos.fmd b/src/mainboard/google/volteer/chromeos.fmd
new file mode 100644
index 0000000..60ea3de
--- /dev/null
+++ b/src/mainboard/google/volteer/chromeos.fmd
@@ -0,0 +1,47 @@
+FLASH@0xfe000000 0x2000000 {
+ SI_ALL@0x0 0x500000 {
+ SI_DESC@0x0 0x1000
+ SI_ME@0x1000 0x4ff000
+ }
+ SI_BIOS@0x500000 0x1b00000 {
+ # Place RW_LEGACY at the start of BIOS region such that the rest
+ # of BIOS regions start at 16MiB boundary. Since this is a 32MiB
+ # SPI flash only the top 16MiB actually gets memory mapped.
+ RW_LEGACY(CBFS)@0x0 0xf00000
+ RW_SECTION_A@0xf00000 0x3e0000 {
+ VBLOCK_A@0x0 0x10000
+ FW_MAIN_A(CBFS)@0x10000 0x3cffc0
+ RW_FWID_A@0x3dffc0 0x40
+ }
+ RW_SECTION_B@0x12e0000 0x3e0000 {
+ VBLOCK_B@0x0 0x10000
+ FW_MAIN_B(CBFS)@0x10000 0x3cffc0
+ RW_FWID_B@0x3dffc0 0x40
+ }
+ RW_MISC@0x16c0000 0x40000 {
+ UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 {
+ RECOVERY_MRC_CACHE@0x0 0x10000
+ RW_MRC_CACHE@0x10000 0x20000
+ }
+ RW_ELOG(PRESERVE)@0x30000 0x4000
+ RW_SHARED@0x34000 0x4000 {
+ SHARED_DATA@0x0 0x2000
+ VBLOCK_DEV@0x2000 0x2000
+ }
+ RW_VPD(PRESERVE)@0x38000 0x2000
+ RW_NVRAM(PRESERVE)@0x3a000 0x6000
+ }
+ # Make WP_RO region align with SPI vendor
+ # memory protected range specification.
+ WP_RO@0x1700000 0x400000 {
+ RO_VPD(PRESERVE)@0x0 0x4000
+ RO_SECTION@0x4000 0x3fc000 {
+ FMAP@0x0 0x800
+ RO_FRID@0x800 0x40
+ RO_FRID_PAD@0x840 0x7c0
+ GBB@0x1000 0x3000
+ COREBOOT(CBFS)@0x4000 0x3f8000
+ }
+ }
+ }
+}
diff --git a/src/mainboard/google/volteer/dsdt.asl b/src/mainboard/google/volteer/dsdt.asl
new file mode 100644
index 0000000..a7d9e6b
--- /dev/null
+++ b/src/mainboard/google/volteer/dsdt.asl
@@ -0,0 +1,87 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include "variant/ec.h"
+#include "variant/gpio.h"
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, // DSDT revision: ACPI v2.0 and up
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20110725 // OEM revision
+)
+{
+ // Some generic macros
+ #include <soc/intel/tigerlake/acpi/platform.asl>
+
+ // global NVS and variables
+ #include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+
+ // CPU
+ #include <cpu/intel/common/acpi/cpu.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+ #include <soc/intel/tigerlake/acpi/southbridge.asl>
+ }
+ }
+
+ Scope (\_SB) {
+ Device (PEPD)
+ {
+ Name (_HID, "INT33A1" /* Intel Power Engine */) // _HID: Hardware ID
+ Name (_CID, EisaId ("PNP0D80") /* System Power Management Controller */) // _CID: Compatible ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (PPD0, Package (0x03)
+ {
+ "\\_SB.PC00.SAT0",
+ Zero,
+ Package (0x02)
+ {
+ Zero,
+ Package (0x03)
+ {
+ 0xFF,
+ Zero,
+ 0x81
+ }
+ }
+ })
+ }
+ }
+
+ // Chrome OS specific
+ #include <vendorcode/google/chromeos/acpi/chromeos.asl>
+
+ // Chrome OS Embedded Controller
+ Scope (\_SB.PCI0.LPCB)
+ {
+ // ACPI code for EC SuperIO functions
+ #include <ec/google/chromeec/acpi/superio.asl>
+ // ACPI code for EC functions
+ #include <ec/google/chromeec/acpi/ec.asl>
+ }
+
+ // Chipset specific sleep states
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
+
+ /* MIPI camera */
+ #include "acpi/mipi_camera.asl"
+}
diff --git a/src/mainboard/google/volteer/ec.c b/src/mainboard/google/volteer/ec.c
new file mode 100644
index 0000000..ab5705e
--- /dev/null
+++ b/src/mainboard/google/volteer/ec.c
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Intel Corp.
+ * Copyright 2019 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <ec/ec.h>
+#include <ec/google/chromeec/ec.h>
+#include <variant/ec.h>
+
+void mainboard_ec_init(void)
+{
+ static const struct google_chromeec_event_info info = {
+ .log_events = MAINBOARD_EC_LOG_EVENTS,
+ .sci_events = MAINBOARD_EC_SCI_EVENTS,
+ .s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS,
+ .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS,
+ .s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS,
+ };
+
+ google_chromeec_events_init(&info, acpi_is_wakeup_s3());
+}
diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c
new file mode 100644
index 0000000..7f77bf5
--- /dev/null
+++ b/src/mainboard/google/volteer/mainboard.c
@@ -0,0 +1,82 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <baseboard/variants.h>
+#include <device/device.h>
+#include <ec/ec.h>
+#include <ec/google/chromeec/ec.h>
+#include <soc/gpio.h>
+#include <smbios.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+#include <variant/gpio.h>
+
+#define SKU_UNKNOWN 0xFFFFFFFF
+#define SKU_MAX 0x7FFFFFFF
+
+static uint32_t get_board_sku(void)
+{
+ static uint32_t sku_id = SKU_UNKNOWN;
+
+ if (sku_id != SKU_UNKNOWN)
+ return sku_id;
+
+ if (google_chromeec_cbi_get_sku_id(&sku_id))
+ sku_id = SKU_UNKNOWN;
+
+ return sku_id;
+}
+
+const char *smbios_system_sku(void)
+{
+ static char sku_str[14]; /* sku{0..2147483647} */
+ uint32_t sku_id = get_board_sku();
+
+ if ((sku_id == SKU_UNKNOWN) || (sku_id > SKU_MAX)) {
+ printk(BIOS_ERR, "%s: Unexpected SKU ID %u\n",
+ __func__, sku_id);
+ return "";
+ }
+
+ snprintf(sku_str, sizeof(sku_str), "sku%u", sku_id);
+
+ return sku_str;
+}
+
+static void mainboard_init(void *chip_info)
+{
+ const struct pad_config *base_pads;
+ const struct pad_config *override_pads;
+ size_t base_num, override_num;
+
+ base_pads = variant_base_gpio_table(&base_num);
+ override_pads = variant_override_gpio_table(&override_num);
+
+ gpio_configure_pads_with_override(base_pads, base_num,
+ override_pads, override_num);
+
+ mainboard_ec_init();
+}
+
+static void mainboard_enable(struct device *dev)
+{
+ dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
+}
+
+struct chip_operations mainboard_ops = {
+ .init = mainboard_init,
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/google/volteer/smihandler.c b/src/mainboard/google/volteer/smihandler.c
new file mode 100644
index 0000000..8b82de6
--- /dev/null
+++ b/src/mainboard/google/volteer/smihandler.c
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cpu/x86/smm.h>
+#include <ec/google/chromeec/smm.h>
+#include <intelblocks/smihandler.h>
+#include <variant/ec.h>
+
+void mainboard_smi_espi_handler(void)
+{
+ chromeec_smi_process_events();
+}
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+ chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS,
+ MAINBOARD_EC_S5_WAKE_EVENTS);
+}
+
+int mainboard_smi_apmc(u8 apmc)
+{
+ chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS,
+ MAINBOARD_EC_SMI_EVENTS);
+ return 0;
+}
diff --git a/src/mainboard/google/volteer/spd/Makefile.inc b/src/mainboard/google/volteer/spd/Makefile.inc
new file mode 100644
index 0000000..93f0f60
--- /dev/null
+++ b/src/mainboard/google/volteer/spd/Makefile.inc
@@ -0,0 +1,35 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2019 Intel Corporation.
+## Copyright 2019 Google LLC
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+SPD_BIN = $(obj)/spd.bin
+
+ifeq ($(SPD_SOURCES),)
+ SPD_DEPS := $(error SPD_SOURCES is not set. Variant must provide this)
+else
+ SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
+endif
+
+# Include spd ROM data
+$(SPD_BIN): $(SPD_DEPS)
+ for f in $+; \
+ do for c in $$(cat $$f | grep -v ^#); \
+ do printf $$(printf '\%o' 0x$$c); \
+ done; \
+ done > $@
+
+cbfs-files-y += spd.bin
+spd.bin-file := $(SPD_BIN)
+spd.bin-type := spd
diff --git a/src/mainboard/google/volteer/spd/samsung-K4U6E3S4AA-MGCL.spd.hex b/src/mainboard/google/volteer/spd/samsung-K4U6E3S4AA-MGCL.spd.hex
new file mode 100644
index 0000000..e1f27fb
--- /dev/null
+++ b/src/mainboard/google/volteer/spd/samsung-K4U6E3S4AA-MGCL.spd.hex
@@ -0,0 +1,32 @@
+23 11 11 0E 15 19 95 08 00 40 00 00 02 21 00 00
+48 00 04 FF 92 55 00 00 8C 00 90 A8 90 C0 08 60
+04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 7F E1 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20
+20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/volteer/variants/baseboard/Makefile.inc b/src/mainboard/google/volteer/variants/baseboard/Makefile.inc
new file mode 100644
index 0000000..f1c6853
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/baseboard/Makefile.inc
@@ -0,0 +1,21 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2019 Google LLC
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+bootblock-y += gpio.c
+
+ramstage-y += gpio.c
+
+smm-y += gpio.c
+
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
new file mode 100755
index 0000000..fe6ed2e
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
@@ -0,0 +1,391 @@
+chip soc/intel/tigerlake
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+
+ # GPE configuration
+ # Note that GPE events called out in ASL code rely on this
+ # route. i.e. If this route changes then the affected GPE
+ # offset bits also need to be changed.
+ register "pmc_gpe0_dw0" = "GPP_C"
+ register "pmc_gpe0_dw1" = "GPP_D"
+ register "pmc_gpe0_dw2" = "GPP_E"
+
+ # FSP configuration
+ register "SaGv" = "SaGv_Disabled"
+ register "SmbusEnable" = "0"
+
+ register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0
+ register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A1
+ register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN
+ register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C Cl
+ register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera
+ register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used
+ register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used
+ register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used
+ register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C Co
+ register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth
+
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port A0
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # USB3/2 Type A port A1
+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN
+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 Camera
+
+ # Enable Pch iSCLK
+ register "pch_isclk" = "1"
+
+ # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
+ register "gen1_dec" = "0x00fc0801"
+ register "gen2_dec" = "0x000c0201"
+ # EC memory map range is 0x900-0x9ff
+ register "gen3_dec" = "0x00fc0901"
+
+ # Enable NVMe PCIE 9 using clk 0
+ register "PcieRpEnable[8]" = "1"
+ register "PcieClkSrcUsage[0]" = "8"
+ register "PcieClkSrcClkReq[0]" = "0"
+
+ # Enable SD Card PCIE 8 using clk 3
+ register "PcieRpEnable[7]" = "1"
+ register "PcieClkSrcUsage[3]" = "7"
+ register "PcieClkSrcClkReq[3]" = "3"
+ register "sdcard_cd_gpio" = "GPP_E11"
+
+ # Enable WLAN PCIE 7 using clk 1
+ register "PcieRpEnable[6]" = "1"
+ register "PcieClkSrcUsage[1]" = "6"
+ register "PcieClkSrcClkReq[1]" = "1"
+
+ # Enable WWAN PCIE 6 using clk 2
+ register "PcieRpEnable[5]" = "1"
+ register "PcieClkSrcUsage[2]" = "5"
+ register "PcieClkSrcClkReq[2]" = "2"
+
+ # Mark SRCCLKREQ pins as unused that are routed for a Non-Clkreq functionality
+ register "PcieClkSrcUsage[4]" = "0xFF"
+ register "PcieClkSrcUsage[5]" = "0xFF"
+ register "PcieClkSrcUsage[6]" = "0xFF"
+
+ # Enable SATA
+ register "SataEnable" = "1"
+ register "SataMode" = "0"
+ register "SataSalpSupport" = "1"
+ register "SataPortsEnable[0]" = "0"
+ register "SataPortsEnable[1]" = "1"
+ register "SataPortsDevSlp[0]" = "0"
+
+ register "SerialIoI2cMode" = "{
+ [PchSerialIoIndexI2C0] = PchSerialIoPci,
+ [PchSerialIoIndexI2C1] = PchSerialIoPci,
+ [PchSerialIoIndexI2C2] = PchSerialIoPci,
+ [PchSerialIoIndexI2C3] = PchSerialIoPci,
+ [PchSerialIoIndexI2C4] = PchSerialIoDisabled,
+ [PchSerialIoIndexI2C5] = PchSerialIoPci,
+ }"
+
+ register "SerialIoGSpiMode" = "{
+ [PchSerialIoIndexGSPI0] = PchSerialIoPci,
+ [PchSerialIoIndexGSPI1] = PchSerialIoPci,
+ [PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
+ [PchSerialIoIndexGSPI3] = PchSerialIoDisabled,
+ }"
+
+ register "SerialIoGSpiCsMode" = "{
+ [PchSerialIoIndexGSPI0] = 1,
+ [PchSerialIoIndexGSPI1] = 1,
+ [PchSerialIoIndexGSPI2] = 0,
+ [PchSerialIoIndexGSPI3] = 0,
+ }"
+
+ register "SerialIoGSpiCsState" = "{
+ [PchSerialIoIndexGSPI0] = 0,
+ [PchSerialIoIndexGSPI1] = 0,
+ [PchSerialIoIndexGSPI2] = 0,
+ [PchSerialIoIndexGSPI3] = 0,
+ }"
+
+ register "SerialIoUartMode" = "{
+ [PchSerialIoIndexUART0] = PchSerialIoPci,
+ [PchSerialIoIndexUART1] = PchSerialIoDisabled,
+ [PchSerialIoIndexUART2] = PchSerialIoDisabled,
+ }"
+
+ #HD Audio /* FIXME - TODO */
+ register "PchHdaDspEnable" = "1"
+ #register "PchHdaAudioLinkHdaEnable" = "0"
+ #register "PchHdaAudioLinkDmicEnable[0]" = "1"
+ #register "PchHdaAudioLinkDmicEnable[1]" = "1"
+ #register "PchHdaAudioLinkSspEnable[0]" = "1"
+ #register "PchHdaAudioLinkSspEnable[1]" = "1"
+ # iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T
+ #register "PchHdaIDispLinkTmode" = "2"
+ # iDisp-Link Freq 4: 96MHz, 3: 48MHz.
+ #register "PchHdaIDispLinkFrequency" = "4"
+ # Not disconnected/enumerable
+ #register "PchHdaIDispCodecDisconnect" = "0"
+
+ # ISH /* FIXME - TODO */
+ #register "PchIshSpiEnable" = "0"
+ #register "PchIshSpiCs0Enable" = "0"
+ #register "PchIshUartEnable[0]" = "0"
+ #register "PchIshUartEnable[1]" = "0"
+ #register "PchIshI2cEnable[0]" = "0"
+ #register "PchIshI2cEnable[1]" = "0"
+ #register "PchIshI2cEnable[2]" = "0"
+ #register "PchIshGpEnable[0]" = "0"
+ #register "PchIshGpEnable[1]" = "0"
+ #register "PchIshGpEnable[2]" = "0"
+ #register "PchIshGpEnable[3]" = "0"
+ #register "PchIshGpEnable[4]" = "0"
+ #register "PchIshGpEnable[5]" = "0"
+ #register "PchIshGpEnable[6]" = "0"
+ #register "PchIshGpEnable[7]" = "0"
+
+ # TCSS USB3 /* FIXME - TODO */
+ #register "TcssXhciEn" = "1"
+ #register "TcssXdciEn" = "1"
+
+ # Image clock setting
+ #register "ImguClkOutEn[0]" = "0"
+ #register "ImguClkOutEn[1]" = "0"
+ #register "ImguClkOutEn[2]" = "1"
+ #register "ImguClkOutEn[3]" = "1"
+ #register "ImguClkOutEn[4]" = "0"
+
+ # DP port
+ register "DdiPortAConfig" = "1"
+ register "DdiPortBConfig" = "0"
+
+ register "DdiPortAHpd" = "1"
+ register "DdiPortBHpd" = "1"
+ register "DdiPortCHpd" = "0"
+ register "DdiPort1Hpd" = "1"
+ register "DdiPort2Hpd" = "1"
+ register "DdiPort3Hpd" = "0"
+ register "DdiPort4Hpd" = "0"
+
+ register "DdiPortADdc" = "0"
+ register "DdiPortBDdc" = "1"
+ register "DdiPortCDdc" = "0"
+ register "DdiPort1Ddc" = "0"
+ register "DdiPort2Ddc" = "0"
+ register "DdiPort3Ddc" = "0"
+ register "DdiPort4Ddc" = "0"
+
+ # Disable PM to allow for shorter irq pulses
+ register "gpio_override_pm" = "1"
+ register "gpio_pm[0]" = "0"
+ register "gpio_pm[1]" = "0"
+ register "gpio_pm[2]" = "0"
+ register "gpio_pm[3]" = "0"
+ register "gpio_pm[4]" = "0"
+
+ # Enable "Intel Speed Shift Technology"
+ register "speed_shift_enable" = "1"
+
+ # Enable S0ix
+ register "s0ix_enable" = "1"
+
+ # Intel Common SoC Config
+ #+-------------------+---------------------------+
+ #| Field | Value |
+ #+-------------------+---------------------------+
+ #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
+ #| GSPI0 | cr50 TPM. Early init is |
+ #| | required to set up a BAR |
+ #| | for TPM communication |
+ #| | before memory is up |
+ #| GSPI1 | Fingerprint MCU
+ #| I2C0 | Audio |
+ #| I2C1 | Touchscreen |
+ #| I2C2 | WLAN, SAR0 |
+ #| I2C3 | Camera, SAR1 |
+ #| I2C5 | Trackpad |
+ #| pch_thermal_trip | PCH Trip Temperature |
+ #+-------------------+---------------------------+
+ register "common_soc_config" = "{
+ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+ .gspi[0] = {
+ .speed_mhz = 1,
+ .early_init = 1,
+ },
+ .i2c[0] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[1] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[2] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[3] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[5] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .pch_thermal_trip = 75,
+ }"
+
+ device domain 0 on
+ #From EDS(575683)
+ device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y
+ device pci 02.0 on end # Graphics
+ device pci 04.0 on end # DPTF 0x9A03
+ device pci 05.0 off end # IPU 0x9A19
+ device pci 06.0 off end # PEG60 0x9A09
+ device pci 07.0 on end # TBT_PCIe0 0x9A23
+ device pci 07.1 on end # TBT_PCIe1 0x9A25
+ device pci 07.2 on end # TBT_PCIe2 0x9A27
+ device pci 07.3 on end # TBT_PCIe3 0x9A29
+ device pci 08.0 on end # GNA 0x9A11
+ device pci 09.0 off end # NPK 0x9A33
+ device pci 0a.0 off end # Crash-log SRAM 0x9A0D
+ device pci 0d.0 on end # USB xHCI 0x9A13
+ device pci 0d.1 off end # USB xDCI (OTG) 0x9A15
+ device pci 0d.2 off end # TBT DMA0 0x9A1B
+ device pci 0d.3 off end # TBT DMA1 0x9A1D
+ device pci 0e.0 off end # VMD 0x9A0B
+
+ # From PCH EDS(576591)
+ device pci 10.0 on end # I2C6 0xA0D8
+ device pci 10.1 off end # I2C7 0xA0D9
+ device pci 10.2 on end # CNVi: BT 0xA0F5 - A0F7
+ device pci 10.6 off end # THC0 0xA0D0
+ device pci 10.7 off end # THC1 0xA0D1
+
+ device pci 11.0 off end # UART3 0xA0DA
+ device pci 11.1 off end # UART4 0xA0DB
+ device pci 11.2 off end # UART5 0xA0DC
+ device pci 11.3 off end # UART6 0xA0DD
+
+ device pci 12.0 off end # SensorHUB 0xA0FC
+ device pci 12.6 off end # GSPI2 0x34FB
+
+ device pci 13.0 off end # GSPI3 0xA0FD
+ device pci 13.1 off end # GSPI4 0xA0FE
+ device pci 13.2 off end # GSPI5 0xA0DE
+ device pci 13.3 off end # GSPI6 0xA0DF
+
+ device pci 14.0 on end # USB3.1 xHCI 0xA0ED
+ device pci 14.1 off end # USB3.1 xDCI 0xA0EE
+ device pci 14.2 on end # Shared RAM 0xA0EF
+ device pci 14.3 on end # CNVi: WiFi 0xA0F0 - A0F3
+
+ device pci 15.0 on
+ chip drivers/i2c/generic
+ register "hid" = ""10EC5682""
+ register "name" = ""RT58""
+ register "desc" = ""Realtek RT5682""
+ register "irq" = "ACPI_IRQ_EDGE_HIGH(GPP_F8_IRQ)"
+ # Set the jd_src to RT5668_JD1 for jack detection
+ register "property_count" = "1"
+ register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
+ register "property_list[0].name" = ""realtek,jd-src""
+ register "property_list[0].integer" = "1"
+ device i2c 1a on end
+ end
+ end # I2C #0 0xA0E8
+ device pci 15.1 on end # I2C1 0xA0E9
+ device pci 15.2 on
+ chip drivers/i2c/sx9310
+ register "desc" = ""SAR0 Proximity Sensor""
+ register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)"
+ register "speed" = "I2C_SPEED_FAST"
+ register "uid" = "0"
+ register "reg_prox_ctrl0" = "0x10"
+ register "reg_prox_ctrl1" = "0x00"
+ register "reg_prox_ctrl2" = "0x84"
+ register "reg_prox_ctrl3" = "0x0e"
+ register "reg_prox_ctrl4" = "0x07"
+ register "reg_prox_ctrl5" = "0xc6"
+ register "reg_prox_ctrl6" = "0x20"
+ register "reg_prox_ctrl7" = "0x0d"
+ register "reg_prox_ctrl8" = "0x8d"
+ register "reg_prox_ctrl9" = "0x43"
+ register "reg_prox_ctrl10" = "0x1f"
+ register "reg_prox_ctrl11" = "0x00"
+ register "reg_prox_ctrl12" = "0x00"
+ register "reg_prox_ctrl13" = "0x00"
+ register "reg_prox_ctrl14" = "0x00"
+ register "reg_prox_ctrl15" = "0x00"
+ register "reg_prox_ctrl16" = "0x00"
+ register "reg_prox_ctrl17" = "0x00"
+ register "reg_prox_ctrl18" = "0x00"
+ register "reg_prox_ctrl19" = "0x00"
+ register "reg_sar_ctrl0" = "0x50"
+ register "reg_sar_ctrl1" = "0x8a"
+ register "reg_sar_ctrl2" = "0x3c"
+ device i2c 28 on end
+ end
+ end # I2C2 0xA0EA
+ device pci 15.3 on end # I2C3 0xA0EB
+
+ device pci 16.0 on end # HECI1 0xA0E0
+ device pci 16.1 off end # HECI2 0xA0E1
+ device pci 16.2 off end # CSME 0xA0E2
+ device pci 16.3 off end # CSME 0xA0E3
+ device pci 16.4 off end # HECI3 0xA0E4
+ device pci 16.5 off end # HECI4 0xA0E5
+
+ device pci 17.0 on end # SATA 0xA0D3
+
+ device pci 19.0 on end # I2C4 0xA0C5
+ device pci 19.1 on
+ chip drivers/i2c/generic
+ register "hid" = ""ELAN0000""
+ register "desc" = ""ELAN Touchpad""
+ register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E15_IRQ)"
+ register "probed" = "1"
+ device i2c 15 on end
+ end
+ end # I2C5 0xA0C6
+ device pci 19.2 off end # UART2 0xA0C7
+
+ device pci 1c.0 on end # RP1 0xA0B8
+ device pci 1c.1 off end # RP2 0xA0B9
+ device pci 1c.2 off end # RP3 0xA0BA
+ device pci 1c.3 off end # RP4 0xA0BB
+ device pci 1c.4 off end # RP5 0xA0BC
+ device pci 1c.5 on end # WWAN RP6 0xA0BD
+ device pci 1c.6 on end # RP7 0xA0BE
+ device pci 1c.7 on end # SD Card RP8 0xA0BF
+
+ device pci 1d.0 on end # RP9 0xA0B0
+ device pci 1d.1 off end # RP10 0xA0B1
+ device pci 1d.2 off end # RP11 0xA0B2
+ device pci 1d.3 off end # RP12 0xA0B3
+ device pci 1d.4 off end # RP13 0xA0B4
+ device pci 1d.5 off end # RP14 0xA0B5
+ device pci 1d.6 off end # RP15 0xA0B6
+ device pci 1d.7 off end # RP16 0xA0B7
+
+ device pci 1e.0 on end # UART0 0xA0A8
+ device pci 1e.1 off end # UART1 0xA0A9
+ device pci 1e.2 on
+ chip drivers/spi/acpi
+ register "hid" = "ACPI_DT_NAMESPACE_HID"
+ register "compat_string" = ""google,cr50""
+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C21_IRQ)"
+ device spi 0 on end
+ end
+ end # GSPI0 0xA0AA
+ device pci 1e.3 on end # GSPI1 0xA0AB
+
+ device pci 1f.0 on end # eSPI 0xA080 - A09F
+ device pci 1f.1 off end # P2SB 0xA0A0
+ device pci 1f.2 on end # PMC 0xA0A1
+ device pci 1f.3 on
+ chip drivers/generic/max98357a
+ register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)"
+ register "sdmode_delay" = "5"
+ device generic 0 on end
+ end
+ end # Intel HD audio 0xA0C8-A0CF
+ device pci 1f.4 off end # SMBus 0xA0A3
+ device pci 1f.5 on end # SPI 0xA0A4
+ device pci 1f.6 off end # GbE 0x15E1/0x15E2
+ device pci 1f.7 off end # TH 0xA0A6
+ end
+end
diff --git a/src/mainboard/google/volteer/variants/baseboard/gpio.c b/src/mainboard/google/volteer/variants/baseboard/gpio.c
new file mode 100644
index 0000000..7093d6a
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/baseboard/gpio.c
@@ -0,0 +1,477 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+
+/* Pad configuration in ramstage */
+/* Leave eSPI pins untouched from default settings */
+static const struct pad_config gpio_table[] = {
+ /* A0 thru A6 come configured out of reset, do not touch */
+ /* A0 : ESPI_IO0 ==> ESPI_IO_0 */
+ /* A1 : ESPI_IO1 ==> ESPI_IO_1 */
+ /* A2 : ESPI_IO2 ==> ESPI_IO_2 */
+ /* A3 : ESPI_IO3 ==> ESPI_IO_3 */
+ /* A4 : ESPI_CS# ==> ESPI_CS_L */
+ /* A5 : ESPI_CLK ==> ESPI_CLK */
+ /* A6 : ESPI_RESET# ==> NC(TP764) */
+ /* A7 : I2S2_SCLK ==> EN_PP3300_TRACKPAD */
+ PAD_CFG_GPO(GPP_A7, 1, DEEP),
+ /* A8 : I2S2_SFRM ==> EN_PP3300_TOUCHSCREEN */
+ PAD_CFG_GPO(GPP_A8, 1, DEEP),
+ /* A9 : I2S2_TXD ==> EC_IN_RW_OD */
+ PAD_CFG_GPI(GPP_A9, NONE, DEEP),
+ /* A10 : I2S2_RXD ==> EN_SPKR_PA */
+ PAD_CFG_GPO(GPP_A10, 1, DEEP),
+ /* A11 : PMC_I2C_SDA ==> SSD_PERST_ODL */
+ PAD_CFG_GPO(GPP_A11, 1, DEEP),
+ /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */
+ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
+ /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */
+ PAD_CFG_GPO(GPP_A13, 1, DEEP),
+ /* A14 : USB_OC1# ==> USB_A0_OC_ODL */
+ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
+ /* A15 : USB_OC2# ==> USB_A1_OC_ODL */
+ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
+ /* A16 : USB_OC3# ==> USB_C0_OC_ODL */
+ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
+ /* A17 : DDSP_HPDC ==> MEM_CH_SEL */
+ PAD_CFG_GPI(GPP_A17, NONE, DEEP),
+ /* A18 : DDSP_HPDB ==> HDMI_HPD */
+ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
+ /* A19 : DDSP_HPD1 ==> USB_C0_DP_HPD */
+ PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),
+ /* A20 : DDSP_HPD2 ==> USB_C1_DP_HPD */
+ PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1),
+ /* A21 : DDPC_CTRCLK ==> EN_FP_PWR */
+ PAD_CFG_GPO(GPP_A21, 1, DEEP),
+ /* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */
+ PAD_CFG_GPO(GPP_A22, 1, DEEP),
+ /* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */
+ PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1),
+
+ /* B0 : CORE_VID0 */
+ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
+ /* B1 : CORE_VID1 */
+ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
+ /* B2 : VRALERT# ==> VRALERT_L */
+ PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1),
+ /* B3 : CPU_GP2 ==> PEN_DET_ODL */
+ PAD_CFG_GPI(GPP_B3, NONE, DEEP),
+ /* B4 : CPU_GP3 ==> NC */
+ PAD_NC(GPP_B4, NONE),
+ /* B5 : ISH_I2C0_CVF_SDA */
+ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
+ /* B6 : ISH_I2C0_CVF_SCL */
+ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
+ /* B7 : ISH_12C1_SDA ==> ISH_I2C0_SENSOR_SDA */
+ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
+ /* B8 : ISH_I2C1_SCL ==> ISH_I2C0_SENSOR_SCL */
+ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
+ /* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */
+ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
+ /* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */
+ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
+ /* B11 : PMCALERT# ==> PCH_WP_OD */
+ PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP),
+ /* B12 : SLP_S0# ==> SLP_S0_L */
+ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+ /* B13 : PLTRST# ==> PLT_RST_L */
+ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+ /* B14 : SPKR ==> GPP_B14_STRAP */
+ PAD_NC(GPP_B14, NONE),
+ /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */
+ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
+ /* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */
+ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
+ /* B17 : GSPI0_MISO ==> PCH_GSPIO_H1_TPM_MISO */
+ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
+ /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */
+ PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1),
+ /* B19 : GSPI1_CS0# ==> PCH_GSPI1_FPMCU_CS_L */
+ PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
+ /* B20 : GSPI1_CLK ==> PCH_GSPI1_FPMCU_CLK */
+ PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1),
+ /* B21 : GSPI1_MISO ==> PCH_GSPI1_FPMCU_MISO */
+ PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1),
+ /* B22 : GSPI1_MOSI ==> PCH_GSPI1_GPMCU_MOSI */
+ PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1),
+ /* B23 : SML1ALERT# ==> GPP_B23_STRAP # */
+ PAD_NC(GPP_B23, DN_20K),
+
+ /* C0 : SMBCLK ==> EN_PP3300_WLAN */
+ PAD_CFG_GPO(GPP_C0, 1, DEEP),
+ /* C1 : SMBDATA ==> NOT USED */
+ PAD_NC(GPP_C1, NONE),
+ /* C2 : SMBALERT# ==> GPP_C2_STRAP */
+ PAD_NC(GPP_C2, DN_20K),
+ /* C3 : SML0CLK ==> USB4_SMB_SCL */
+ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
+ /* C4 : SML0DATA ==> USB4_SMB_SDA */
+ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
+ /* C5 : SML0ALERT# ==> USB_SMB_INT_L_BOOT_STRAP0 */
+ PAD_NC(GPP_C5, DN_20K),
+ /* C6 : SML1CLK ==> EC_PCH_INT_ODL */
+ PAD_CFG_GPI_SCI_LOW(GPP_C6, NONE, PLTRST, EDGE_SINGLE),
+ /* C7 : SML1DATA ==> EN_USI_CHARGE */
+ PAD_CFG_GPO(GPP_C7, 1, DEEP),
+ /* C8 : UART0_RXD ==> UART_PCH_RX_DEBUG_TX */
+ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
+ /* C9 : UART0_TXD ==> UART_PCH_TX_DEBUG_RX */
+ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
+ /* C10 : UART0_RTS# ==> USI_RST_L */
+ PAD_CFG_GPO(GPP_C10, 1, DEEP),
+ /* C11 : UART0_CTS# ==> CVF_LPSS_INT_L */
+ PAD_CFG_GPI(GPP_C11, NONE, DEEP),
+ /* C12 : UART1_RXD ==> MEM_STRAP_0 */
+ PAD_CFG_GPI(GPP_C12, NONE, DEEP),
+ /* C13 : UART1_TXD ==> EN_PP5000_TRACKPAD */
+ PAD_CFG_GPO(GPP_C13, 1, DEEP),
+ /* C14 : UART1_RTS# ==> MEM_STRAP_2 */
+ PAD_CFG_GPI(GPP_C14, NONE, DEEP),
+ /* C15 : UART1_CTS# ==> MEM_STRAP_1 */
+ PAD_CFG_GPI(GPP_C15, NONE, DEEP),
+ /* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */
+ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
+ /* C17 : I2C0_SCL ==> PCH_I2C0_1V8_AUDIO_SCL */
+ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
+ /* C18 : I2C1_SDA ==> PCH_I2C1_TOUCH_USI_SDA */
+ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
+ /* C19 : I2C1_SCL ==> PCH_I2C1_TOUCH_USI_SCL */
+ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
+ /* C20 : UART2_RXD ==> FPMCU_INT_L */
+ PAD_CFG_GPI_SCI_LOW(GPP_C20, NONE, PLTRST, EDGE_SINGLE),
+ /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */
+ PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT),
+ /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */
+ PAD_CFG_GPO(GPP_C22, 0, DEEP),
+ /* C23 : UART2_CTS# ==> FPMCU_RST_ODL */
+ PAD_CFG_GPO(GPP_C23, 1, DEEP),
+
+ /* D0 : ISH_GP0 ==> ISH_IMU_INT_L */
+ PAD_NC(GPP_D0, UP_20K),
+ /* D1 : ISH_GP1 ==> ISH_ACCEL_INT_L */
+ PAD_CFG_GPI(GPP_D1, UP_20K, DEEP),
+ /* D2 : ISH_GP2 ==> ISH_LID_OPEN */
+ PAD_CFG_GPI(GPP_D2, UP_20K, DEEP),
+ /* D3 : ISH_GP3 ==> ISH_ALS_RGB_INT_L */
+ PAD_CFG_GPI(GPP_D3, UP_20K, DEEP),
+ /* D4 : IMGCLKOUT0 ==> FCAM_RST_L */
+ PAD_CFG_GPO(GPP_D4, 0, PLTRST),
+ /* D5 : SRCCLKREQ0$ ==> SSD_CLKREQ_ODL */
+ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
+ /* D6 : SRCCLKREQ1# ==> WLAN_CLKREQ_ODL */
+ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
+ /* D7 : SRCCLKREQ2# ==> WWAN_CLKREQ_ODL */
+ PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
+ /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */
+ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
+ /* D9 : ISH_SPI_CS# ==> PCH_GSPI2_CVF_CS_L */
+ PAD_CFG_NF(GPP_D9, NONE, DEEP, NF7),
+ /* D10 : ISH_SPI_CLK ==> PCH_GSPI2_CVF_CLK_STRAP */
+ PAD_CFG_NF(GPP_D10, DN_20K, DEEP, NF7),
+ /* D11 : ISH_SPI_MISO ==> PCH_GSPI2_CVF_MISO */
+ PAD_CFG_NF(GPP_D11, NONE, DEEP, NF7),
+ /* D12 : ISH_SPI_MOSI ==> PCH_GSPI2_CVF_MISO_STRAP */
+ PAD_CFG_NF(GPP_D12, DN_20K, DEEP, NF7),
+ /* D13 : ISH_UART0_RXD ==> UART_ISH_RX_DEBUG_TX */
+ PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
+ /* D14 : ISH_UART0_TXD ==> UART_ISH_TX_DEBUG_RX */
+ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
+ /* D15 : ISH_UART0_RTS# ==> MEM_STRAP_3 */
+ PAD_CFG_GPI(GPP_D15, NONE, DEEP),
+ /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */
+ PAD_CFG_GPO(GPP_D16, 1, DEEP),
+ /* D17 : ISH_GP4 ==> EN_FCAM_PWR */
+ PAD_CFG_GPO(GPP_D17, 1, DEEP),
+ /* D18 : ISH_GP5 ==> FCAM_SNRPWR_EN */
+ PAD_CFG_GPO(GPP_D18, 1, DEEP),
+ /* D19 : I2S_MCLK1 ==> I2S_MCLK1 */
+ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
+
+ /* E0 : SATAXPCIE0 ==> USB_A1_RT_RST_ODL */
+ PAD_CFG_GPO(GPP_E0, 1, DEEP),
+ /* E1 : SPI1_IO2 ==> PEN_DET_ODL */
+ PAD_CFG_GPI_SCI_LOW(GPP_E1, NONE, DEEP, EDGE_SINGLE),
+ /* E2 : SPI1_IO3 ==> WLAN_PCIE_WAKE_ODL */
+ PAD_CFG_GPI(GPP_E2, NONE, DEEP),
+ /* E3 : CPU_GP0 ==> USI_REPORT_EN */
+ PAD_CFG_GPO(GPP_E3, 1, DEEP),
+ /* E4 : SATA_DEVSLP0 ==> M2_SSD_PE_WAKE_ODL */
+ PAD_NC(GPP_E4, NONE),
+ /* E5 : SATA_DEVSLP1 ==> M2_SSD_DEVSLP_OD */
+ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),
+ /* E6 : THC0_SPI1_RST# ==> GPPE6_STRAP */
+ PAD_NC(GPP_E6, NONE),
+ /* E7 : CPU_GP1 ==> USI_INT */
+ PAD_CFG_GPI(GPP_E7, NONE, DEEP),
+ /* E8 : SPI1_CS1# ==> SLP_S0IX */
+ PAD_CFG_GPO(GPP_E8, 0, DEEP),
+ /* E9 : USB2_OC0# ==> USB_C1_OC_ODL */
+ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
+ /* E10 : SPI1_CS# ==> USB_C0_AUXP_DC */
+ PAD_CFG_GPO(GPP_E10, 0, DEEP),
+ /* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */
+ PAD_CFG_GPI(GPP_E11, NONE, DEEP),
+ /* E12 : SPI1_MISO_IO1 ==> NOT USED */
+ PAD_NC(GPP_E12, NONE),
+ /* E13 : SPI1_MOSI_IO0 ==> USB_C0_AUXN_DC */
+ PAD_CFG_GPO(GPP_E13, 0, DEEP),
+ /* E14 : DDPC_HPDA ==> SOC_EDP_HPD */
+ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
+ /* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */
+ PAD_CFG_GPI_APIC(GPP_E15, NONE, PLTRST, LEVEL, INVERT),
+ /* E16 : ISH_GP7 ==> WWAN_SIM1_DET_OD */
+ PAD_CFG_GPI(GPP_E16, NONE, DEEP),
+ /* E17 : THC0_SPI1_INT# ==> WWAN_PERST_L */
+ PAD_CFG_TERM_GPO(GPP_E17, 1, DN_20K, DEEP),
+ /* E18 : DDP1_CTRLCLK ==> USB_C0_LSX_SOC_TX */
+ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4),
+ /* E19 : DDP1_CTRLDATA ==> USB0_C0_LSX_SOC_RX_STRAP */
+ PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF4),
+ /* E20 : DDP2_CTRLCLK ==> USB_C1_LSX_SOC_TX */
+ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF4),
+ /* E21 : DDP2_CTRLDATA ==> USB_C1_LSX_SOC_RX_STRAP */
+ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4),
+ /* E22 : DDPA_CTRLCLK ==> USB_C1_AUXP_DC: Retimer FW drives this pin */
+ PAD_NC(GPP_E22, NONE),
+ /* E23 : DDPA_CTRLDATA ==> USB_C1_AUXN_DC: Retimer FW drives this pin */
+ PAD_NC(GPP_E23, NONE),
+
+ /* F0 : CNV_BRI_DT ==> CNV_BRI_DT_STRAP */
+ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
+ /* F1 : CNV_BRI_RSP ==> NCV_BRI_RSP */
+ PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1),
+ /* F2 : I2S2_TXD ==> CNV_RGI_DT_STRAP */
+ PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
+ /* F3 : I2S2_RXD ==> CNV_RGI_RSP */
+ PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1),
+ /* F4 : CNV_RF_RESET# ==> CNV_RF_RST_L */
+ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
+ /* F5 : MODEM_CLKREQ ==> CNV_CLKREQ0 */
+ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF3),
+ /* F6 : CNV_PA_BLANKING ==> WWAN_WLAN_COEX3 */
+ PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
+ /* F7 : GPPF7_STRAP */
+ PAD_NC(GPP_F7, DN_20K),
+ /* F8 : I2S_MCLK2_INOUT ==> HP_INT_L */
+ PAD_CFG_GPI_APIC(GPP_F8, UP_20K, DEEP, EDGE_BOTH, INVERT),
+ /* F9 : Reserved ==> NC */
+ /* F10 : GPPF10_STRAP */
+ PAD_NC(GPP_F10, DN_20K),
+ /* F11 : THC1_SPI2_CLK ==> EN_PP3300_WWAN */
+ PAD_CFG_GPO(GPP_F11, 1, DEEP),
+ /* F12 : GSXDOUT ==> WWAN_RST_ODL */
+ PAD_CFG_GPO(GPP_F12, 1, DEEP),
+ /* F13 : GSXDOUT ==> WiFi_DISABLE_L */
+ PAD_CFG_GPO(GPP_F13, 1, DEEP),
+ /* F14 : GSXDIN ==> SAR0_INT_L */
+ PAD_CFG_GPI_SCI_LOW(GPP_F14, NONE, PLTRST, EDGE_SINGLE),
+ /* F15 : GSXSRESET# ==> RCAM_RST_L */
+ PAD_CFG_GPO(GPP_F15, 1, DEEP),
+ /* PAD_CFG_GPI_SCI_LOW(GPP_F15, NONE, PLTRST, EDGE_SINGLE), */
+ /* F16 : GSXCLK ==> WWAN_DPR_SAR_ODL */
+ PAD_CFG_GPO(GPP_F16, 1, DEEP),
+ /* F17 : WWAN_RF_DISABLE_ODL */
+ PAD_CFG_GPO(GPP_F17, 1, DEEP),
+ /* F18 : THC1_SPI2_INT# ==> WWAN_PCIE_WAKE_ODL */
+ PAD_CFG_GPI_SCI_LOW(GPP_F18, NONE, DEEP, EDGE_SINGLE),
+ /* F19 : SRCCLKREQ6# ==> WLAN_INT_L */
+ PAD_CFG_GPI_SCI_LOW(GPP_F19, NONE, DEEP, EDGE_SINGLE),
+ /* F20 : EXT_PWR_GATE# ==> EXT_PWR_GATE_L */
+ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
+ /* F21 : EXT_PWR_GATE2# ==> EXT_PWR_GATE2_L */
+ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
+ /* F22 : VNN_CTRL */
+ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
+ /* F23 : V1P05_CTRL */
+ PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1),
+
+ /* H0 : GPPH0_BOOT_STRAP1 */
+ PAD_NC(GPP_H0, DN_20K),
+ /* H1 : GPPH1_BOOT_STRAP2 */
+ PAD_NC(GPP_H1, DN_20K),
+ /* H2 : GPPH2_BOOT_STRAP3 */
+ PAD_NC(GPP_H2, DN_20K),
+ /* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */
+ PAD_CFG_GPO(GPP_H3, 1, DEEP),
+ /* H4 : I2C2_SDA ==> PCH_I2C2_MISC_SDA */
+ PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
+ /* H5 : I2C2_SCL ==> PCH_I2C2_MISC_SCL */
+ PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
+ /* H6 : I2C3_SDA ==> PCH_I2C3_CAM_SDA */
+ PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
+ /* H7 : I2C3_SCL ==> PCH_I2C3_CAM_SCL */
+ PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
+ /* H8 : I2C4_SDA ==> WWAN_WLAN_COEX1 */
+ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2),
+ /* H9 : I2C4_SCL ==> WWAN_WLAN_COEX2 */
+ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2),
+ /* H10 : SRCCLKREQ4# ==> USB_C1_RT_FORCE_PWR */
+ PAD_CFG_GPO(GPP_H10, 1, DEEP),
+ /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */
+ PAD_CFG_GPO(GPP_H11, 1, DEEP),
+ /* H12 : M2_SKT2_CFG0 ==> WWAN_CONFIG0 */
+ PAD_CFG_GPI(GPP_H12, NONE, DEEP),
+ /* H13 : M2_SKT2_CFG1 # ==> WWAN_CONFIG1 */
+ PAD_CFG_GPI(GPP_H13, NONE, DEEP),
+ /* H14 : M2_SKT2_CFG2 # ==> RCAM_SNRPWR_EN */
+ PAD_CFG_GPO(GPP_H14, 1, DEEP),
+ /* H15 : M2_SKT2_CFG3 # ==> WWAN_CONFIG3 */
+ PAD_CFG_GPI(GPP_H15, NONE, DEEP),
+ /* H16 : DDPB_CTRLCLK ==> DDPB_HDMI_CTRLCLK */
+ PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1),
+ /* H17 : DDPB_CTRLDATA ==> DDPB_HDMI_CTRLDATA */
+ PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
+ /* H18 : CPU_C10_GATE# ==> CPU_C10_GATE_L */
+ PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
+ /* H19 : TIME_SYNC0 ==> USER_PRES_FP_ODL */
+ PAD_CFG_GPI(GPP_H19, NONE, DEEP),
+ /* H20 : IMGCLKOUT1 ==> EN_MIPI_RCAM_PWR */
+ PAD_CFG_GPO(GPP_H20, 1, PLTRST),
+ /* H21 : IMGCLKOUT2 ==> CAM_MCLK1 */
+ PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
+ /* H22 : IMGCLKOUT3 ==> CAM_MCLK0 */
+ PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
+ /* H23 : IMGCLKOUT4 ==> WWAN_ESIM_SEL_ODL */
+ PAD_CFG_GPO(GPP_H23, 1, DEEP),
+
+ /* R0 : HDA_BCLK ==> I2S0_HP_SCLK */
+ PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2),
+ /* R1 : HDA_SYNC ==> I2S0_HP_SFRM */
+ PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2),
+ /* R2 : HDA_SDO ==> I2S0_PCH_TX_HP_RX_STRAP */
+ PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2),
+ /* R3 : HDA_SDIO ==> I2S0_PCH_RX_HP_TX */
+ PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2),
+ /* R4 : HDA_RST# ==> HDA_RST_L */
+ PAD_CFG_NF(GPP_R4, DN_20K, DEEP, NF1),
+ /* R5 : HDA_SDI1 ==> I2S1_PCH_RX_SPKR_TX */
+ PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2),
+ /* R6 : I2S1_TXD ==> I2S1_PCH_RX_SPKR_RX */
+ PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2),
+ /* R7 : I2S1_SFRM ==> I2S1_SPKR_SFRM */
+ PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2),
+
+ /* S0 : SNDW0_CLK ==> SNDW0_HP_CLK */
+ PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1),
+ /* S1 : SNDW0_DATA ==> SNDW0_HP_DATA */
+ PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1),
+ /* S2 : SNDW1_CLK ==> SNDW1_SPKR_CLK */
+ PAD_CFG_NF(GPP_S2, NONE, DEEP, NF1),
+ /* S3 : SNDW1_DATA ==> SNDW1_SPKR_DATA */
+ PAD_CFG_NF(GPP_S3, NONE, DEEP, NF1),
+ /* S4 : SNDW2_CLK ==> DMIC_CLK1 */
+ PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2),
+ /* S5 : SNDW2_DATA ==> DMIC_DATA1 */
+ PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2),
+ /* S6 : SNDW3_CLK ==> DMIC_CLK0 */
+ PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2),
+ /* S7 : SNDW3_DATA ==> DMIC_DATA0 */
+ PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2),
+
+ /* GPD0: BATLOW# ==> BATLOW_L */
+ PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
+ /* GPD1: ACPRESENT ==> PCH_ACPRESENT */
+ PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
+ /* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_ODL */
+ PAD_CFG_GPI(GPD2, NONE, DEEP),
+ /* GPD3: PWRBTN# ==> EC_PCH_PWR_BTN_ODL */
+ PAD_CFG_NF(GPD3, NONE, DEEP, NF1),
+ /* GPD4: SLP_S3# ==> SLP_S3_L */
+ PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
+ /* GPD5: SLP_S4# ==> SLP_S4_L */
+ PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
+ /* GPD6: SLP_A# ==> SLP_A_L */
+ PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
+ /* GPD7: GPD7_STRAP */
+ PAD_CFG_GPI(GPD7, DN_20K, DEEP),
+ /* GPD8: SUSCLK ==> PCH_SUSCLK */
+ PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
+ /* GPD9: SLP_WLAN# ==> SLP_WLAN_L */
+ PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
+ /* GPD10: SLP_S5# ==> SLP_S5_L */
+ PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
+ /* GPD11: LANPHYC ==> NC */
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+ /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */
+ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
+
+ /* A17 : DDSP_HPDC ==> MEM_CH_SEL */
+ PAD_CFG_GPI(GPP_A17, NONE, DEEP),
+
+ /* B11 : PMCALERT# ==> PCH_WP_OD */
+ PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP),
+
+ /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */
+ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
+
+ /* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */
+ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
+
+ /* B17 : GSPI0_MISO ==> PCH_GSPIO_H1_TPM_MISO */
+ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
+
+ /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */
+ PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1),
+
+ /* C0 : SMBCLK ==> EN_PP3300_WLAN */
+ PAD_CFG_GPO(GPP_C0, 1, DEEP),
+
+ /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */
+ PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT),
+
+ /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */
+ PAD_CFG_GPO(GPP_C22, 0, DEEP),
+
+ /* E12 : SPI1_MISO_IO1 ==> EN_PP3300_SSD */
+ PAD_CFG_GPO(GPP_E12, 1, DEEP),
+
+ /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */
+ PAD_CFG_GPO(GPP_H11, 1, RSMRST),
+};
+
+const struct pad_config *__weak variant_base_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(gpio_table);
+ return gpio_table;
+}
+
+const struct pad_config *__weak variant_override_gpio_table(size_t *num)
+{
+ *num = 0;
+ return NULL;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(early_gpio_table);
+ return early_gpio_table;
+}
+
+static const struct cros_gpio cros_gpios[] = {
+ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_COMM1_NAME),
+ CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_COMM1_NAME),
+};
+
+const struct cros_gpio *__weak variant_cros_gpios(size_t *num)
+{
+ *num = ARRAY_SIZE(cros_gpios);
+ return cros_gpios;
+}
diff --git a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/ec.h
new file mode 100644
index 0000000..85d521c
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/ec.h
@@ -0,0 +1,82 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MAINBOARD_EC_H__
+#define __MAINBOARD_EC_H__
+
+#include <ec/ec.h>
+#include <ec/google/chromeec/ec_commands.h>
+#include <variant/gpio.h>
+
+#define MAINBOARD_EC_SCI_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX))
+
+#define MAINBOARD_EC_SMI_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
+
+/* EC can wake from S5 with lid or power button */
+#define MAINBOARD_EC_S5_WAKE_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
+
+/* EC can wake from S3 with lid, power button or mode change event */
+#define MAINBOARD_EC_S3_WAKE_EVENTS \
+ (MAINBOARD_EC_S5_WAKE_EVENTS |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
+
+#define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS)
+
+/* Log EC wake events plus EC shutdown events */
+#define MAINBOARD_EC_LOG_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
+
+/*
+ * ACPI related definitions for ASL code.
+ */
+
+/* Enable EC backed ALS device in ACPI */
+#define EC_ENABLE_ALS_DEVICE
+
+/* Enable LID switch and provide wake pin for EC */
+#define EC_ENABLE_LID_SWITCH
+#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE
+
+/* Enable Tablet switch */
+#define EC_ENABLE_TBMC_DEVICE
+
+#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */
+#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */
+#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */
+
+/* Enable EC sync interrupt, EC_SYNC_IRQ is defined in variant/gpio.h */
+#define EC_ENABLE_SYNC_IRQ
+
+#endif /* __MAINBOARD_EC_H__ */
diff --git a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/gpio.h
new file mode 100644
index 0000000..35212a3
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/gpio.h
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __BASEBOARD_GPIO_H__
+#define __BASEBOARD_GPIO_H__
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+/* EC in RW */
+#define GPIO_EC_IN_RW GPP_A9
+
+/* BIOS Flash Write Protect */
+#define GPIO_PCH_WP GPP_B11
+
+/* Memory configuration board straps */
+#define GPIO_MEM_CONFIG_0 GPP_C12
+#define GPIO_MEM_CONFIG_1 GPP_C15
+#define GPIO_MEM_CONFIG_2 GPP_C14
+#define GPIO_MEM_CONFIG_3 GPP_D15
+
+/* EC wake is LAN_WAKE# */
+#define GPE_EC_WAKE GPE0_LAN_WAK
+
+/* EC sync IRQ */
+#define EC_SYNC_IRQ GPP_C6_IRQ
+
+/* eSPI virtual wire reporting */
+#define EC_SCI_GPI GPE0_ESPI
+
+/* DRAM population strap (value 0=fully-populated, 1=half-populated) */
+#define GPIO_MEM_CH_SEL GPP_A17
+
+#endif /* BASEBOARD_GPIO_H */
diff --git a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h
new file mode 100644
index 0000000..8801ecd
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __BASEBOARD_VARIANTS_H__
+#define __BASEBOARD_VARIANTS_H__
+
+#include <soc/gpio.h>
+#include <soc/meminit.h>
+#include <stdint.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+/*
+ * The next set of functions return the gpio table and fill in the number of
+ * entries for each table.
+ */
+const struct pad_config *variant_base_gpio_table(size_t *num);
+const struct pad_config *variant_early_gpio_table(size_t *num);
+const struct pad_config *variant_override_gpio_table(size_t *num);
+
+const struct cros_gpio *variant_cros_gpios(size_t *num);
+
+void variant_memory_params(struct mb_lpddr4x_cfg *bcfg);
+int variant_memory_sku(void);
+
+#endif /* __BASEBOARD_VARIANTS_H__ */
diff --git a/src/mainboard/google/volteer/variants/volteer/Makefile.inc b/src/mainboard/google/volteer/variants/volteer/Makefile.inc
new file mode 100644
index 0000000..ad968c7
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/volteer/Makefile.inc
@@ -0,0 +1,17 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2019 Google LLC
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+## Memory Options
+SPD_SOURCES = samsung-K4U6E3S4AA-MGCL # 0b0000
diff --git a/src/mainboard/google/volteer/variants/volteer/include/variant/acpi/dptf.asl b/src/mainboard/google/volteer/variants/volteer/include/variant/acpi/dptf.asl
new file mode 100644
index 0000000..4f6497a
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/volteer/include/variant/acpi/dptf.asl
@@ -0,0 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/acpi/dptf.asl>
diff --git a/src/mainboard/google/volteer/variants/volteer/include/variant/ec.h b/src/mainboard/google/volteer/variants/volteer/include/variant/ec.h
new file mode 100644
index 0000000..260d7d4
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/volteer/include/variant/ec.h
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_EC_H
+#define MAINBOARD_EC_H
+
+#include <baseboard/ec.h>
+
+#endif
diff --git a/src/mainboard/google/volteer/variants/volteer/include/variant/gpio.h b/src/mainboard/google/volteer/variants/volteer/include/variant/gpio.h
new file mode 100644
index 0000000..750b0d4
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/volteer/include/variant/gpio.h
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+#include <baseboard/gpio.h>
+
+#endif /* MAINBOARD_GPIO_H */
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