Weiyi Lu would like Weiyi Lu to review this change.

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WIP: mediatek/mt8183: update dcxo setting

Disable unused DCXO and power mode.

BRANCH=none
TEST=Boots correctly on Kukui.

Change-Id: I2e5ce181ad327ccf852979da53baca4f249912fe
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
M src/soc/mediatek/mt8183/include/soc/rtc.h
M src/soc/mediatek/mt8183/rtc.c
2 files changed, 4 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/32323/1

diff --git a/src/soc/mediatek/mt8183/include/soc/rtc.h b/src/soc/mediatek/mt8183/include/soc/rtc.h
index 3d115fe..a721ff8 100644
--- a/src/soc/mediatek/mt8183/include/soc/rtc.h
+++ b/src/soc/mediatek/mt8183/include/soc/rtc.h
@@ -140,6 +140,7 @@
 	PMIC_RG_DCXO_CW15 = 0x07AE,
 	PMIC_RG_DCXO_CW16 = 0x07B0,
 	PMIC_RG_DCXO_CW21 = 0x07BA,
+	PMIC_RG_DCXO_CW23 = 0x07BE,
 	PMIC_RG_DCXO_ELR0 = 0x07C4
 };
 
diff --git a/src/soc/mediatek/mt8183/rtc.c b/src/soc/mediatek/mt8183/rtc.c
index 62256eb..57f26e8 100644
--- a/src/soc/mediatek/mt8183/rtc.c
+++ b/src/soc/mediatek/mt8183/rtc.c
@@ -281,9 +281,10 @@
 	rtc_write(PMIC_RG_DCXO_CW16, 0x9855);
 
 	/* 26M enable control */
-	/* Enable clock buffer XO_SOC, XO_CEL */
-	rtc_write(PMIC_RG_DCXO_CW00, 0x4805);
+	/* Enable clock buffer XO_SOC */
+	rtc_write(PMIC_RG_DCXO_CW00, 0x4005);
 	rtc_write(PMIC_RG_DCXO_CW11, 0x8000);
+	rtc_write(PMIC_RG_DCXO_CW23, 0x0053);
 
 	/* Load thermal coefficient */
 	rtc_write(PMIC_RG_TOP_TMA_KEY, 0x9CA7);

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