Werner Zeh has uploaded this change for review.
intel/block/cpu: Keep flash region cached until the payload is loaded
Since FSP version 2.1 EFI_MP_SERVICES_PPI can be used to bring up all
the APs. For some SOCs it is mandatory that MP init is done by FSP
in order to have the full features enabled (e.g. Elkhart Lake or Alder
Lake). If the MP init is done by FSP, early MTRR setup is done by FSP,
too. Later in the boot flow, in BS_WRITE_TABLES exit, the MTRR setup is
re-configured by coreboot native code based on the registered resources.
This is done before payload is loaded. Now, in this scenario, the SPI
flash linear address range is not registered as a resource (since the
common SPI driver in src/soc/intel/common/block/spi is shared across
multiple SPI controllers and therefore cannot distinguish where the
flash is actually located at). This in turn leads to an uncached flash
range when coreboot re-configures the MTRRs. The result of this chain is
that loading the payload from flash takes much longer now (on mc_ehl1 it
takes ~12 seconds for 4.5 MB).
This patch adds a call to 'fast_spi_cache_bios_region()' right after the
MTRR setup has been performed by coreboot. With this call a temporary
MTRR region will be added that covers the flash range which will
accelerate the payload loading a lot (on mc_ehl1 now to ~4 seconds).
The call to 'fast_spi_cache_bios_region()' has to be done after MTRR
setup as otherwise there will be no free variable MTRR slot available
due to the missing initialization of the MTRR structure.
Here is the timestamp portion showing the payload load time as a
comparison between current upstream and the patched version:
upstream:
90:starting to load payload 1,072,459 (1,802)
958:calling FspNotify(ReadyToBoot) 12,818,079 (11,745,619)
with this patch:
90:starting to load payload 1,072,663 (2,627)
958:calling FspNotify(ReadyToBoot) 5,299,535 (4,226,871)
Change-Id: If19beaefc8fd3bbbe4b181820993abcd882bbbe1
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
---
M src/soc/intel/common/block/cpu/mp_init.c
1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/62566/1
diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c
index 8f220a8..eb69489 100644
--- a/src/soc/intel/common/block/cpu/mp_init.c
+++ b/src/soc/intel/common/block/cpu/mp_init.c
@@ -160,6 +160,9 @@
{
if (mp_run_on_all_cpus(&wrapper_x86_setup_mtrrs, NULL) != CB_SUCCESS)
printk(BIOS_ERR, "MTRR programming failure\n");
+ /* Make sure SPI flash region stays cached to load the payload fast. */
+ if (CONFIG(MP_SERVICES_PPI) && CONFIG(SOC_INTEL_COMMON_BLOCK_FAST_SPI))
+ fast_spi_cache_bios_region();
x86_mtrr_check();
}
To view, visit change 62566. To unsubscribe, or for help writing mail filters, visit settings.