Arthur Heymans uploaded patch set #5 to this change.

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[WIP,TESTONLY]soc/intel/icelake: Use SSDT generator to generate PCI _PRT table

This creates a _PRT ACPI table using the common southbridge code based
on the default routes the FSP sets up.

TODO: soc/irq.h can be cleaned up and adapted with this code in mind.

The working DSDT version is not removed so that the SSDT version can
be debugged.

Change-Id: I44687e9d18a8fd2c926022fdae1240339df1c978
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
---
M src/soc/intel/icelake/Kconfig
M src/soc/intel/icelake/Makefile.inc
M src/soc/intel/icelake/chip.c
A src/soc/intel/icelake/pirq.c
M src/southbridge/intel/common/Kconfig
5 files changed, 87 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/36437/5

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I44687e9d18a8fd2c926022fdae1240339df1c978
Gerrit-Change-Number: 36437
Gerrit-PatchSet: 5
Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz>
Gerrit-Reviewer: Arthur Heymans <arthur@aheymans.xyz>
Gerrit-Reviewer: Martin Roth <martinroth@google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com>
Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org>
Gerrit-Reviewer: Subrata Banik <subrata.banik@intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>
Gerrit-MessageType: newpatchset