Bruce Griffith (Bruce.Griffith@se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3781
-gerrit
commit 334df15f2297f68fff8949978aed2e19ac459dc6 Author: Siyuan Wang wangsiyuanbuaa@gmail.com Date: Tue Jul 9 17:08:41 2013 +0800
AMD Kabini: Add CPU AGESA wrapper for new AMD processor family
Change-Id: I4a1d2118aeb2895f3c2acea5e792fbd69c855156 Reviewed-by: Marc Jones marc.jones@se-eng.com Signed-off-by: Bruce Griffith Bruce.Griffith@se-eng.com Reviewed-by: Mike Loptien mike.loptien@se-eng.com Tested-by: Bruce Griffith bruce.griffith@se-eng.com --- src/cpu/amd/agesa/Kconfig | 2 + src/cpu/amd/agesa/Makefile.inc | 1 + src/cpu/amd/agesa/family16kb/Kconfig | 73 +++++ src/cpu/amd/agesa/family16kb/Makefile.inc | 445 +++++++++++++++++++++++++++ src/cpu/amd/agesa/family16kb/chip_name.c | 24 ++ src/cpu/amd/agesa/family16kb/model_16_init.c | 133 ++++++++ src/include/cpu/amd/amdfam16.h | 47 +++ 7 files changed, 725 insertions(+)
diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index c660470..142ba8e 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -24,6 +24,7 @@ config CPU_AMD_AGESA default y if CPU_AMD_AGESA_FAMILY14 default y if CPU_AMD_AGESA_FAMILY15 default y if CPU_AMD_AGESA_FAMILY15_TN + default y if CPU_AMD_AGESA_FAMILY16_KB default n select TSC_SYNC_LFENCE select UDELAY_LAPIC @@ -55,5 +56,6 @@ source src/cpu/amd/agesa/family12/Kconfig source src/cpu/amd/agesa/family14/Kconfig source src/cpu/amd/agesa/family15/Kconfig source src/cpu/amd/agesa/family15tn/Kconfig +source src/cpu/amd/agesa/family16kb/Kconfig
endif # CPU_AMD_AGESA diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc index b5f39d6..dbdfba9 100644 --- a/src/cpu/amd/agesa/Makefile.inc +++ b/src/cpu/amd/agesa/Makefile.inc @@ -21,6 +21,7 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY12) += family12 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += family14 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15) += family15 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) += family15tn +subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += family16kb
romstage-$(CONFIG_HAVE_ACPI_RESUME) += s3_resume.c ramstage-$(CONFIG_HAVE_ACPI_RESUME) += s3_resume.c diff --git a/src/cpu/amd/agesa/family16kb/Kconfig b/src/cpu/amd/agesa/family16kb/Kconfig new file mode 100644 index 0000000..9a8bce2 --- /dev/null +++ b/src/cpu/amd/agesa/family16kb/Kconfig @@ -0,0 +1,73 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +config CPU_AMD_AGESA_FAMILY16_KB + bool + select PCI_IO_CFG_EXT + select X86_AMD_FIXED_MTRRS + +if CPU_AMD_AGESA_FAMILY16_KB + +config CPU_ADDR_BITS + int + default 40 + +config CPU_SOCKET_TYPE + hex + default 0x10 + +# DDR2 and REG +config DIMM_SUPPORT + hex + default 0x0104 + +config EXT_RT_TBL_SUPPORT + bool + default n + +config EXT_CONF_SUPPORT + bool + default n + +config CBB + hex + default 0x0 + +config CDB + hex + default 0x18 + +config XIP_ROM_BASE + hex + default 0xfff80000 + +config XIP_ROM_SIZE + hex + default 0x100000 + +config HAVE_INIT_TIMER + bool + default y + +config HIGH_SCRATCH_MEMORY_SIZE + hex + # Assume the maximum size of stack as (0xA0000 - 0x30000 + 0x1000) + default 0xA1000 + +endif diff --git a/src/cpu/amd/agesa/family16kb/Makefile.inc b/src/cpu/amd/agesa/family16kb/Makefile.inc new file mode 100644 index 0000000..f21459a --- /dev/null +++ b/src/cpu/amd/agesa/family16kb/Makefile.inc @@ -0,0 +1,445 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +ramstage-y += chip_name.c +ramstage-y += model_16_init.c + +AGESA_ROOT = ../../../../vendorcode/amd/agesa/f16kb + +agesa_lib_src = +agesa_lib_src += $(AGESA_ROOT)/Legacy/Proc/agesaCallouts.c +agesa_lib_src += $(AGESA_ROOT)/Legacy/Proc/Dispatcher.c +agesa_lib_src += $(AGESA_ROOT)/Legacy/Proc/hobTransfer.c +agesa_lib_src += $(AGESA_ROOT)/Lib/amdlib.c +agesa_lib_src += $(AGESA_ROOT)/Lib/helper.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitEarly.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitEnv.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitLate.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitMid.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitPost.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitReset.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitResume.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdLateRunApTask.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdS3LateRestore.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdS3Save.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Common/CommonInits.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Common/CommonReturns.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Common/CreateStruct.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Common/S3RestoreState.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Common/S3SaveState.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cahaltasm.S +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cahalt.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuApicUtilities.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuBist.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuEarlyInit.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuEventLog.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuFamilyTranslation.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuGeneralServices.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuLateInit.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuMicrocodePatch.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuPostInit.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuPowerMgmt.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuPowerMgmtSingleSocket.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuWarmReset.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x16/cpuF16Apm.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x16/cpuF16BrandId.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x16/cpuF16CacheDefaults.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x16/cpuF16Dmi.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x16/cpuF16MmioMap.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x16/cpuF16MsrUnknownTables.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x16/cpuF16PciUnknownTables.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x16/cpuF16Utilities.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x16/cpuF16WheaInitDataTables.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x16/KB/F16KbC6State.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x16/KB/F16KbCacheFlushOnHalt.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x16/KB/F16KbCoreAfterReset.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x16/KB/F16KbCpb.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x16/KB/F16KbDmi.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x16/KB/F16KbEquivalenceTable.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x16/KB/F16KbHtc.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x16/KB/F16KbInitEarlyTable.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x16/KB/F16KbIoCstate.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x16/KB/F16KbLogicalIdTables.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x16/KB/F16KbMicrocodePatch0700002A_Enc.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x16/KB/F16KbMicrocodePatch07000106_Enc.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x16/KB/F16KbMicrocodePatchTables.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x16/KB/F16KbMsrTables.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x16/KB/F16KbNbAfterReset.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x16/KB/F16KbPciTables.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x16/KB/F16KbPowerCheck.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x16/KB/F16KbPowerMgmtSystemTables.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x16/KB/F16KbPsi.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x16/KB/F16KbPstate.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x16/KB/F16KbSharedMsrTable.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x16/KB/F16KbUtilities.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuApm.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuC6State.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuCacheFlushOnHalt.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuCacheInit.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuCdit.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuCoreLeveling.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuCpb.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuCrat.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuDmi.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuFeatureLeveling.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuFeatures.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuHtc.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuIoCstate.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuPsi.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuPstateGather.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuPstateLeveling.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuPstateTables.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuSlit.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuSrat.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuWhea.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/heapManager.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/S3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Table.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Common/GnbLibFeatures.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtEarly.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtEnv.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtLate.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtMid.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtPost.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtReset.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtS3Save.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLib.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbTimerLib.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbFamTranslation/GnbTranslation.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxConfig/GfxConfigMid.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxIntTableV3/GfxIntegratedInfoTable.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxIntTableV3/GfxLibV3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxIntTableV3/GfxPwrPlayTable.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitKB/AlibKB.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitKB/GfxEnvInitKB.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitKB/GfxGmcInitKB.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitKB/GfxIntegratedInfoTableKB.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitKB/GfxIntegratedInfoTableKB.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitKB/GfxLibKB.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitKB/GfxMidInitKB.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitKB/GfxPostInitKB.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitKB/GfxSamuInitKB.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitKB/GfxTablesKB.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitKB/GnbEarlyInitKB.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitKB/GnbEnvInitKB.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitKB/GnbF1TableKB.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitKB/GnbIommuTablesKB.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitKB/GnbMidInitKB.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitKB/GnbPostInitKB.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitKB/GnbRegisterAccKB.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitKB/GnbTablesKB.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitKB/GnbUraKB.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitKB/GnbUraKB.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitKB/GnbUraTokenMapKB.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitKB/PcieComplexDataKB.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitKB/PcieConfigKB.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitKB/PcieEarlyInitKB.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitKB/PcieEnvInitKB.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitKB/PcieLibKB.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitKB/PcieMidInitKB.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitKB/PciePostInitKB.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitKB/PcieTablesKB.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbIoapic/GnbIoapic.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbNbInitLibV5/GnbNbInitLibV5.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieAlibV2/PcieAlibV2.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieAspm/PcieAspm.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieClkPm/PcieClkPm.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV4/PciePortServicesV4.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV4/PcieWrapperServicesV4.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV5/PciePhyServicesV5.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV5/PciePifServicesV5.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV5/PciePortServicesV5.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV5/PcieSiliconServicesV5.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV5/PcieTopologyServicesV5.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV5/PcieWrapperServicesV5.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieMaxPayload/PcieMaxPayload.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieTrainingV2/PcieTrainingV2.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieTrainingV2/PcieWorkaroundsV2.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbSbLib/GnbSbLib.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbScsLibV1/GnbScsLibV1.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbSmuLibV7/GnbSmuInitLibV7.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbSSocketLib/GnbSSocketLib.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbSview/GnbSview.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbTable/GnbTable.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbUraLibV1/GnbUraLibV1.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/Fam16/htNbFam16.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/Fam16/htNbUtilitiesFam16.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htFeat.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htInterface.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htInterfaceCoherent.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htInterfaceGeneral.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htInterfaceNonCoherent.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htMain.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htNb.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htNotify.c +agesa_lib_src += $(AGESA_ROOT)/Proc/IDS/Debug/IdsDebug.c +agesa_lib_src += $(AGESA_ROOT)/Proc/IDS/Debug/IdsDebugPrint.c +agesa_lib_src += $(AGESA_ROOT)/Proc/IDS/Debug/IdsDpHdtout.c +agesa_lib_src += $(AGESA_ROOT)/Proc/IDS/Debug/IdsDpSerial.c +agesa_lib_src += $(AGESA_ROOT)/Proc/IDS/Family/0x16/KB/IdsF16KbAllService.c +agesa_lib_src += $(AGESA_ROOT)/Proc/IDS/Library/IdsLib.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ardk/ma.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/CSINTLV/mfcsi.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/DMI/mfDMI.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/ECC/mfecc.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/ECC/mfemp.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/IDENDIMM/mfidendimm.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/LVDDR3/mflvddr3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/MEMCLR/mfmemclr.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/PARTRN/mfParallelTraining.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/PARTRN/mfStandardTraining.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/RDWR2DTRAINING/KB/mfRdWr2DKb.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/RDWR2DTRAINING/mfRdDqs2DTraining.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/RDWR2DTRAINING/mfRdWr2DEyeRimSearch.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/RDWR2DTRAINING/mfRdWr2DPatternGeneration.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/RDWR2DTRAINING/mfRdWr2DTraining.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/S3/mfs3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/TABLE/mftds.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/KB/mmflowkb.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mdef.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/merrhdl.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/minit.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mm.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmConditionalPso.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmEcc.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmExcludeDimm.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmflow.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmLvDdr3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmMemClr.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmMemRestore.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmNodeInterleave.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmOnlineSpare.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmParallelTraining.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmStandardTraining.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmUmaAlloc.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mu.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/muc.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/KB/mndctkb.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/KB/mnflowkb.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/KB/mnidendimmkb.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/KB/mnkb.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/KB/mnmctkb.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/KB/mnotkb.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/KB/mnphykb.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/KB/mnregkb.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/KB/mns3kb.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mn.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mndct.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnfeat.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnflow.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnmct.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnphy.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnreg.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnS3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mntrain3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/KB/FT3/mpSkbft3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/KB/mpkb3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/KB/mpSkb3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/KB/mpUkb3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/mp.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/mpmaxfreq.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/mpmr0.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/mpodtpat.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/mprtt.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/mps2d.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/mpsao.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mt3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mtot3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mtrci3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mtsdi3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mtspd3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mttecc3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mttwl3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mt.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mthdi.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttdimbt.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttecc.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttEdgeDetect.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mtthrc.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mtthrcSeedTrain.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttml.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttoptsrc.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttRdDqs2DEyeRimSearch.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttRdDqs2DTraining.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttsrc.c + +agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Azalia/AzaliaEnv.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Azalia/AzaliaLate.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Azalia/AzaliaMid.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Azalia/AzaliaReset.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Common/AcpiLib.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Common/FchCommon.c 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+= $(AGESA_ROOT)/Proc/Fch/Sata/RaidLate.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/RaidLib.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/RaidMid.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/SataEnv.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/SataEnvLib.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/SataIdeEnv.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/SataIdeLate.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/SataIdeLib.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/SataIdeMid.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/SataLate.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/SataLib.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/SataMid.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/SataReset.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sd/Family/Yangtze/YangtzeSdEnvService.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sd/Family/Yangtze/YangtzeSdResetService.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sd/Family/Yangtze/YangtzeSdService.c +agesa_lib_src += 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+agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/OhciReset.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/UsbEnv.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/UsbLate.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/UsbMid.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/UsbReset.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/XhciEnv.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/XhciLate.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/XhciMid.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/XhciReset.c + + +romstage-y += $(agesa_lib_src) +ramstage-y += $(agesa_lib_src) + +subdirs-y += ../../mtrr +subdirs-y += ../../../x86/tsc +subdirs-y += ../../../x86/lapic +subdirs-y += ../../../x86/cache +subdirs-y += ../../../x86/mtrr +subdirs-y += ../../../x86/pae +subdirs-y += ../../../x86/smm diff --git a/src/cpu/amd/agesa/family16kb/chip_name.c b/src/cpu/amd/agesa/family16kb/chip_name.c new file mode 100644 index 0000000..70dbf59 --- /dev/null +++ b/src/cpu/amd/agesa/family16kb/chip_name.c @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> + +struct chip_operations cpu_amd_agesa_family16kb_ops = { + CHIP_NAME("AMD CPU Family 16h") +}; diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c new file mode 100644 index 0000000..2964b78 --- /dev/null +++ b/src/cpu/amd/agesa/family16kb/model_16_init.c @@ -0,0 +1,133 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> +#include <device/device.h> +#include <device/pci.h> +#include <string.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/pae.h> +#include <pc80/mc146818rtc.h> +#include <cpu/x86/lapic.h> + +#include <cpu/cpu.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/mtrr.h> +#include <cpu/amd/amdfam16.h> +#include <arch/acpi.h> +#if CONFIG_HAVE_ACPI_RESUME +#include <cpu/amd/agesa/s3_resume.h> +#endif + +static void model_16_init(device_t dev) +{ + printk(BIOS_DEBUG, "Model 16 Init.\n"); + + u8 i; + msr_t msr; + int msrno; +#if CONFIG_LOGICAL_CPUS + u32 siblings; +#endif + + //x86_enable_cache(); + //amd_setup_mtrrs(); + //x86_mtrr_check(); + disable_cache (); + /* Enable access to AMD RdDram and WrDram extension bits */ + msr = rdmsr(SYSCFG_MSR); + msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; + msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn; + wrmsr(SYSCFG_MSR, msr); + + // BSP: make a0000-bffff UC, c0000-fffff WB, same as OntarioApMtrrSettingsList for APs + msr.lo = msr.hi = 0; + wrmsr (0x259, msr); + msr.lo = msr.hi = 0x1e1e1e1e; + wrmsr(0x250, msr); + wrmsr(0x258, msr); + for (msrno = 0x268; msrno <= 0x26f; msrno++) + wrmsr (msrno, msr); + + msr = rdmsr(SYSCFG_MSR); + msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; + msr.lo |= SYSCFG_MSR_MtrrFixDramEn; + wrmsr(SYSCFG_MSR, msr); + +#if CONFIG_HAVE_ACPI_RESUME + if (acpi_slp_type == 3) + restore_mtrr(); +#endif + + x86_mtrr_check(); + x86_enable_cache(); + + /* zero the machine check error status registers */ + msr.lo = 0; + msr.hi = 0; + for (i = 0; i < 6; i++) { + wrmsr(MCI_STATUS + (i * 4), msr); + } + + + /* Enable the local cpu apics */ + setup_lapic(); + +#if CONFIG_LOGICAL_CPUS + siblings = cpuid_ecx(0x80000008) & 0xff; + + if (siblings > 0) { + msr = rdmsr_amd(CPU_ID_FEATURES_MSR); + msr.lo |= 1 << 28; + wrmsr_amd(CPU_ID_FEATURES_MSR, msr); + + msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); + msr.hi |= 1 << (33 - 32); + wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); + } + printk(BIOS_DEBUG, "siblings = %02d, ", siblings); +#endif + + /* DisableCf8ExtCfg */ + msr = rdmsr(NB_CFG_MSR); + msr.hi &= ~(1 << (46 - 32)); + wrmsr(NB_CFG_MSR, msr); + + + /* Write protect SMM space with SMMLOCK. */ + msr = rdmsr(HWCR_MSR); + msr.lo |= (1 << 0); + wrmsr(HWCR_MSR, msr); +} + +static struct device_operations cpu_dev_ops = { + .init = model_16_init, +}; + +static struct cpu_device_id cpu_table[] = { + { X86_VENDOR_AMD, 0x700f00 }, /* KB-A0 */ + { 0, 0 }, +}; + +static const struct cpu_driver model_15 __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +}; diff --git a/src/include/cpu/amd/amdfam16.h b/src/include/cpu/amd/amdfam16.h new file mode 100644 index 0000000..7097372 --- /dev/null +++ b/src/include/cpu/amd/amdfam16.h @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef CPU_AMD_FAM16_H +#define CPU_AMD_FAM16_H + +#include <cpu/x86/msr.h> + +#define MCI_STATUS 0x00000401 +#define HWCR_MSR 0xC0010015 +#define NB_CFG_MSR 0xC001001f + +#define LS_CFG_MSR 0xC0011020 +#define IC_CFG_MSR 0xC0011021 +#define DC_CFG_MSR 0xC0011022 +#define CU_CFG_MSR 0xC0011023 +#define CU_CFG2_MSR 0xC001102A + +#define CPU_ID_FEATURES_MSR 0xC0011004 +#define CPU_ID_EXT_FEATURES_MSR 0xC0011005 + +#if defined(__PRE_RAM__) +void wait_all_core0_started(void); +void wait_all_other_cores_started(u32 bsp_apicid); +void wait_all_aps_started(u32 bsp_apicid); +void allow_all_aps_stop(u32 bsp_apicid); +#endif +u32 get_initial_apicid(void); +void get_bus_conf(void); + +#endif /* CPU_AMD_FAM16_H */