Jeremy Soller has uploaded this change for review.

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soc/intel/cannonlake: Set FSP-S Enable8254ClockGating using clock_gate_8254 devicetree parameter

Change-Id: Id346173ac7ae5246de0b38b9dd23be7b72e70f1e
---
M src/soc/intel/cannonlake/fsp_params.c
1 file changed, 4 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/31534/1

diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index c276c86..534065f 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -128,6 +128,10 @@
 	/* S0ix */
 	params->PchPmSlpS0Enable = config->s0ix_enable;
 
+	/* Legacy 8254 timer support */
+	params->Enable8254ClockGating = config->clock_gate_8254;
+	params->Enable8254ClockGatingOnS3 = config->clock_gate_8254;
+
 	/* disable Legacy PME */
 	memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));
 

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