Patrick Georgi merged this change.
soc/intel/cannonlake: Add FSP UPD to unlock GPIO pads in devicetree
FSP has a UPD to unlock all GPIO pads. This parameter is disabled by
default. Add a chip parameter so that GPIO pads can be unlocked on mainboard
level in devicetree and therefore this feature can be used if needed.
BUG=b:128686027
Change-Id: Iad9e8a209dc3f8ca0c994e8c1da329918409a1d4
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32110
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
---
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/fsp_params.c
2 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index a81a7c1..7461d78 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -407,6 +407,9 @@
uint8_t DdiPortCDdc;
uint8_t DdiPortDDdc;
uint8_t DdiPortFDdc;
+
+ /* Unlock all GPIO Pads */
+ uint8_t PchUnlockGpioPads;
};
typedef struct soc_intel_cannonlake_config config_t;
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index 25ee5e1..2688557 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -340,6 +340,9 @@
/* Set TccActivationOffset */
tconfig->TccActivationOffset = config->tcc_offset;
+
+ /* Unlock all GPIO pads */
+ tconfig->PchUnlockGpioPads = config->PchUnlockGpioPads;
}
/* Mainboard GPIO Configuration */
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