Patrick Rudolph has uploaded this change for review.
sb/intel/lynxpoint: Use common AHCI
Untested.
Change-Id: I9c46e85084996b430b077f4bc683a96df42bf41a
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
---
M src/southbridge/intel/lynxpoint/Kconfig
M src/southbridge/intel/lynxpoint/sata.c
2 files changed, 5 insertions(+), 27 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/37139/1
diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig
index ef071f2..03b9bbb 100644
--- a/src/southbridge/intel/lynxpoint/Kconfig
+++ b/src/southbridge/intel/lynxpoint/Kconfig
@@ -21,6 +21,7 @@
config SOUTH_BRIDGE_OPTIONS # dummy
def_bool y
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
+ select SOUTHBRIDGE_INTEL_COMMON_AHCI
select SOUTHBRIDGE_INTEL_COMMON_SMBUS
select SOUTHBRIDGE_INTEL_COMMON_SPI
select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT
diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c
index 75bfbde..911575b 100644
--- a/src/southbridge/intel/lynxpoint/sata.c
+++ b/src/southbridge/intel/lynxpoint/sata.c
@@ -21,6 +21,8 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <delay.h>
+#include <southbridge/intel/common/ahci.h>
+
#include "chip.h"
#include "pch.h"
@@ -94,8 +96,6 @@
pci_write_config32(dev, 0x94,
((config->sata_port_map ^ 0x3f) << 24) | 0x183);
} else if (config->sata_ahci) {
- u32 *abar;
-
printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n");
/* Set Interrupt Line */
@@ -154,31 +154,8 @@
pci_write_config32(dev, 0x94, reg32);
/* Initialize AHCI memory-mapped space */
- abar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5);
- printk(BIOS_DEBUG, "ABAR: %p\n", abar);
- /* CAP (HBA Capabilities) : enable power management */
- reg32 = read32(abar + 0x00);
- reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS
- reg32 &= ~0x00020060; // clear SXS+EMS+PMS
- if (pch_is_lp())
- reg32 |= (1 << 18); // SAM: SATA AHCI MODE ONLY
- write32(abar + 0x00, reg32);
- /* PI (Ports implemented) */
- write32(abar + 0x03, config->sata_port_map);
- (void) read32(abar + 0x03); /* Read back 1 */
- (void) read32(abar + 0x03); /* Read back 2 */
- /* CAP2 (HBA Capabilities Extended)*/
- reg32 = read32(abar + 0x09);
- /* Enable DEVSLP */
- if (pch_is_lp()) {
- if (config->sata_devslp_disable)
- reg32 &= ~(1 << 3);
- else
- reg32 |= (1 << 5)|(1 << 4)|(1 << 3)|(1 << 2);
- } else {
- reg32 &= ~0x00000002;
- }
- write32(abar + 0x09, reg32);
+ sb_ahci_init(dev, config->sata_port_map, pch_is_lp(), false, 0,
+ pch_is_lp() && !config->sata_devslp_disable, 0);
} else {
printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n");
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