Xiang Wang uploaded patch set #8 to this change.
riscv: workaround selfboot putting the coreboot table into prog_entry_arg
On RISC-V the argument to a payload is always the hartid and a pointer to a FDT.
selfboot sets the coreboot tables as an argument, work around this here.
Change-Id: If6929897c7f12d8acb079eeebaef512ae506ca8b
Signed-off-by: Xiang Wang <wxjstz@126.com>
---
M src/arch/riscv/boot.c
1 file changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/31477/8
To view, visit change 31477. To unsubscribe, or for help writing mail filters, visit settings.