Patrick Georgi submitted this change.
mb/lenovo/t430s: Open PCIe port #5 for Thunderbolt controller
Some T430s variants have a Thunderbolt controller wired to PCIe port
The controller hotplugs itself to the chipset when a downstream device
is hotplugged into it, so the hotplug capability should be enabled on
PCIe port #5.
TODO: find the correct gpio pin to detect the Thunderbolt controller
at runtime.
There are 3 variants of mainboard for Thinkpad T430s: Basic type
(Wistron LSN-4 11263-1), Boards with an additional discreet GPU,
Boards with an additional TB controller (Wistron LSN-4 11271-1),
each of which has a different schematic.
The gpio27 on the last type is set as set as GPIO-INPUT, compared
with GPIO-OUTPUT-HIGH on the basic type boards.
Change-Id: I61f41db100f398069e50e2da8a378b3a8d1c84bf
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
---
M src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb
1 file changed, 5 insertions(+), 0 deletions(-)
diff --git a/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb b/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb
index ff30702..ee94979 100644
--- a/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb
+++ b/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb
@@ -1,6 +1,11 @@
chip northbridge/intel/sandybridge
device domain 0 on
chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
+ # Enable hotplug on Port 5 for Thunderbolt controller
+ register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 1, 0, 0, 0 }"
+ device pci 1c.4 on
+ subsystemid 0x17aa 0x21fb
+ end # PCIe Port #5 Thunderbolt controller
device pci 1f.0 on
chip ec/lenovo/h8
register "has_bdc_detection" = "1"
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