Nicholas Sudsgaard has uploaded this change for review.
WIP: mainboard/lenovo: Add ThinkCentre M710s
Working:
- Can boot Ubuntu using payloads: SeaBIOS, TianoCore EDK 2
- PCIe
- M2 SSD
- SATA
- USB
- LAN
- CPU fan
- VGA (DP bridge)
- COM1
- TPM
- Memory card reader (Technically just a USB)
- Display ports
- Audio (headphone jack, via display)
- M2 WLAN (+ Bluetooth)
Not Working / Not Tested:
- Audio (internal, works when headphones are connected to the rear port??)
- PCIe clock related things and AER issues (these issues only appear on the LiveCD)
- SuperIO related things
- SATA acpi error?
- libgfxinit some drm issue when using EDK 2
- Internal flashing
Won't Test:
- COM2 header
- LPT header
- PS/2 keyboard and mouse
Change-Id: I551753aecfbd2c0ee57d85bb22cb943eb21af3cc
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
---
A src/mainboard/lenovo/thinkcentre_m710s/Kconfig
A src/mainboard/lenovo/thinkcentre_m710s/Kconfig.name
A src/mainboard/lenovo/thinkcentre_m710s/Makefile.mk
A src/mainboard/lenovo/thinkcentre_m710s/acpi/ec.asl
A src/mainboard/lenovo/thinkcentre_m710s/acpi/superio.asl
A src/mainboard/lenovo/thinkcentre_m710s/board_info.txt
A src/mainboard/lenovo/thinkcentre_m710s/bootblock.c
A src/mainboard/lenovo/thinkcentre_m710s/data.vbt
A src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb
A src/mainboard/lenovo/thinkcentre_m710s/dsdt.asl
A src/mainboard/lenovo/thinkcentre_m710s/early_init.c
A src/mainboard/lenovo/thinkcentre_m710s/gma-mainboard.ads
A src/mainboard/lenovo/thinkcentre_m710s/gpio.h
A src/mainboard/lenovo/thinkcentre_m710s/hda_verb.c
A src/mainboard/lenovo/thinkcentre_m710s/romstage.c
15 files changed, 620 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/80343/1
diff --git a/src/mainboard/lenovo/thinkcentre_m710s/Kconfig b/src/mainboard/lenovo/thinkcentre_m710s/Kconfig
new file mode 100644
index 0000000..9aecf24
--- /dev/null
+++ b/src/mainboard/lenovo/thinkcentre_m710s/Kconfig
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+if BOARD_LENOVO_THINKCENTRE_M710S
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ROMSIZE_KB_8192
+ select SOC_INTEL_KABYLAKE
+ select SKYLAKE_SOC_PCH_H
+ select HAVE_ACPI_TABLES
+ select HAVE_ACPI_RESUME
+ select INTEL_GMA_HAVE_VBT
+ select MAINBOARD_HAS_LIBGFXINIT
+ select SUPERIO_ITE_IT8629E
+ select MAINBOARD_HAS_TPM2
+ select MEMORY_MAPPED_TPM
+
+config MAINBOARD_DIR
+ default "lenovo/thinkcentre_m710s"
+
+config MAINBOARD_PART_NUMBER
+ default "ThinkCentre M710s"
+
+endif # BOARD_LENOVO_THINKCENTRE_M710S
diff --git a/src/mainboard/lenovo/thinkcentre_m710s/Kconfig.name b/src/mainboard/lenovo/thinkcentre_m710s/Kconfig.name
new file mode 100644
index 0000000..5a78582
--- /dev/null
+++ b/src/mainboard/lenovo/thinkcentre_m710s/Kconfig.name
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config BOARD_LENOVO_THINKCENTRE_M710S
+ bool "ThinkCentre M710s"
diff --git a/src/mainboard/lenovo/thinkcentre_m710s/Makefile.mk b/src/mainboard/lenovo/thinkcentre_m710s/Makefile.mk
new file mode 100644
index 0000000..5224305
--- /dev/null
+++ b/src/mainboard/lenovo/thinkcentre_m710s/Makefile.mk
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += early_init.c
+bootblock-y += bootblock.c
+
+ramstage-y += early_init.c
+ramstage-y += hda_verb.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/lenovo/thinkcentre_m710s/acpi/ec.asl b/src/mainboard/lenovo/thinkcentre_m710s/acpi/ec.asl
new file mode 100644
index 0000000..16990d4
--- /dev/null
+++ b/src/mainboard/lenovo/thinkcentre_m710s/acpi/ec.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: CC-PDDC */
+
+/* Please update the license if adding licensable material. */
diff --git a/src/mainboard/lenovo/thinkcentre_m710s/acpi/superio.asl b/src/mainboard/lenovo/thinkcentre_m710s/acpi/superio.asl
new file mode 100644
index 0000000..16990d4
--- /dev/null
+++ b/src/mainboard/lenovo/thinkcentre_m710s/acpi/superio.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: CC-PDDC */
+
+/* Please update the license if adding licensable material. */
diff --git a/src/mainboard/lenovo/thinkcentre_m710s/board_info.txt b/src/mainboard/lenovo/thinkcentre_m710s/board_info.txt
new file mode 100644
index 0000000..8379586
--- /dev/null
+++ b/src/mainboard/lenovo/thinkcentre_m710s/board_info.txt
@@ -0,0 +1,7 @@
+Category: desktop
+Board URL: https://psref.lenovo.com/syspool/Sys/PDF/ThinkCentre/ThinkCentre_M710_SFF/ThinkCentre_M710_SFF_Spec.pdf
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
+Release year: 2017
diff --git a/src/mainboard/lenovo/thinkcentre_m710s/bootblock.c b/src/mainboard/lenovo/thinkcentre_m710s/bootblock.c
new file mode 100644
index 0000000..77b0a96
--- /dev/null
+++ b/src/mainboard/lenovo/thinkcentre_m710s/bootblock.c
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+
+#include "gpio.h"
+
+void bootblock_mainboard_init(void)
+{
+ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
diff --git a/src/mainboard/lenovo/thinkcentre_m710s/data.vbt b/src/mainboard/lenovo/thinkcentre_m710s/data.vbt
new file mode 100644
index 0000000..4855687
--- /dev/null
+++ b/src/mainboard/lenovo/thinkcentre_m710s/data.vbt
Binary files differ
diff --git a/src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb b/src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb
new file mode 100644
index 0000000..ad3c8a5c2
--- /dev/null
+++ b/src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb
@@ -0,0 +1,190 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+# Model: IB250MH
+# Untested:
+# - COM2
+# - LPT
+# - PS/2 Keyboard and Mouse
+# - F_USB1
+# - SYS_FAN, AUX1_FAN, AUX2_FAN
+
+chip soc/intel/skylake
+ # FSP Configuration
+ register "eist_enable" = "true"
+
+ device cpu_cluster 0 on end
+ device domain 0 on
+ device ref system_agent on end
+ device ref peg0 on # PCIE16X
+ register "PcieRpClkReqSupport[0]" = "true"
+ register "PcieRpClkReqNumber[0]" = "2"
+ register "PcieRpClkSrcNumber[0]" = "0"
+ end
+ device ref igpu on end
+ device ref south_xhci on
+ register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # USB30 A
+ register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # USB30 B
+ register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # F_USB30_1 A
+ register "usb2_ports[3]" = "USB2_PORT_MID(OC2)" # F_USB30_1 B
+ register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # F_USB30_2 A
+ register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # F_USB30_2 B
+ register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth
+ register "usb2_ports[7]" = "USB2_PORT_MID(OC5)" # USB_LAN A
+ register "usb2_ports[8]" = "USB2_PORT_MID(OC5)" # USB_LAN B
+ register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # F_USB1 (Pins 5, 7)
+ register "usb2_ports[10]" = "USB2_PORT_MID(OC_SKIP)" # F_USB1 (Pins 6, 8)
+ # Used by the SD/MMC reader.
+ register "usb2_ports[11]" = "USB2_PORT_MID(OC_SKIP)" # F_USB2 (Pins 5, 7)
+
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB30 A
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # USB30 B
+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # F_USB30_1 A
+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)" # F_USB30_1 B
+ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC3)" # F_USB30_2 A
+ register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC3)" # F_USB30_2 B
+ end
+ device ref thermal on end
+ device ref heci1 on end
+ device ref sata on
+ register "SataMode" = "SATA_AHCI"
+ register "SataSalpSupport" = "true"
+ register "SataPortsEnable[0]" = "true" # SATA1
+ register "SataPortsEnable[1]" = "true" # SATA2
+ register "SataPortsEnable[2]" = "true" # SATA3
+ end
+ device ref pcie_rp5 on # USB_LAN
+ register "PcieRpEnable[4]" = "true"
+ register "PcieRpLtrEnable[4]" = "true"
+ register "PcieRpClkReqSupport[4]" = "false"
+ register "PcieRpClkSrcNumber[4]" = "5"
+ register "PcieRpAdvancedErrorReporting[4]" = "true"
+ end
+ device ref pcie_rp7 on # PCIE1X_2
+ register "PcieRpEnable[6]" = "true"
+ register "PcieRpLtrEnable[6]" = "true"
+ register "PcieRpClkReqSupport[6]" = "true"
+ register "PcieRpClkReqNumber[6]" = "7"
+ register "PcieRpClkSrcNumber[6]" = "7"
+ register "PcieRpAdvancedErrorReporting[6]" = "true"
+ end
+ device ref pcie_rp8 on # PCIE1X_1
+ register "PcieRpEnable[7]" = "true"
+ register "PcieRpLtrEnable[7]" = "true"
+ register "PcieRpClkReqSupport[7]" = "true"
+ register "PcieRpClkReqNumber[7]" = "8"
+ register "PcieRpClkSrcNumber[7]" = "8"
+ register "PcieRpAdvancedErrorReporting[7]" = "true"
+ end
+ device ref pcie_rp11 on # M2_WIFI
+ register "PcieRpEnable[10]" = "true"
+ register "PcieRpLtrEnable[10]" = "true"
+ register "PcieRpClkReqSupport[10]" = "true"
+ register "PcieRpClkReqNumber[10]" = "1"
+ register "PcieRpClkSrcNumber[10]" = "1"
+ register "PcieRpAdvancedErrorReporting[10]" = "true"
+ end
+ device ref pcie_rp21 on # M2_SSD
+ register "PcieRpEnable[20]" = "true"
+ register "PcieRpLtrEnable[20]" = "true"
+ register "PcieRpClkReqSupport[20]" = "true"
+ register "PcieRpClkReqNumber[20]" = "6"
+ register "PcieRpClkSrcNumber[20]" = "2"
+ register "PcieRpAdvancedErrorReporting[20]" = "true"
+ end
+ device ref lpc_espi on
+ register "serirq_mode" = "SERIRQ_CONTINUOUS"
+
+ chip superio/ite/it8629e
+ # CPU_FAN
+ register "FAN1.mode" = "FAN_SMART_AUTOMATIC"
+ register "FAN1.smart.tmpin" = "1"
+ register "FAN1.smart.tmp_off" = "35"
+ register "FAN1.smart.tmp_start" = "60"
+ register "FAN1.smart.tmp_full" = "85"
+ register "FAN1.smart.tmp_delta" = "2"
+ register "FAN1.smart.pwm_start" = "20"
+ register "FAN1.smart.slope" = "24"
+
+ register "FAN2.mode" = "FAN_MODE_OFF" # SYS_FAN
+ register "FAN3.mode" = "FAN_MODE_OFF" # AUX1_FAN
+ # FIXME: Add support for 6 fans.
+ #register "FAN6.mode" = "FAN_MODE_OFF" # AUX2_FAN
+
+ register "ec.vin_mask" = "VIN_ALL"
+
+ register "TMPIN1.mode" = "THERMAL_RESISTOR"
+ register "TMPIN2.mode" = "THERMAL_MODE_DISABLED"
+ register "TMPIN3.mode" = "THERMAL_DIODE"
+
+ # Vendor values dumped using util/superiotool.
+ device pnp 2e.0 off end
+ device pnp 2e.1 on # COM1
+ io 0x60 = 0x03f8
+ irq 0x70 = 0x04
+ irq 0xf1 = 0x50
+ end
+ device pnp 2e.2 off end
+ device pnp 2e.3 off end
+ device pnp 2e.4 on
+ io 0x60 = 0x0a30
+ io 0x62 = 0x0230
+ irq 0x70 = 0x09
+ irq 0xf0 = 0x40
+ end
+ device pnp 2e.5 on # KB_MS (PS/2 Keyboard)
+ io 0x60 = 0x0060
+ io 0x62 = 0x0064
+ irq 0x70 = 0x01
+ irq 0x71 = 0x02
+ irq 0xf0 = 0x48
+ end
+ device pnp 2e.6 on # KB_MS (PS/2 Mouse)
+ irq 0x70 = 0x0c
+ irq 0x71 = 0x02
+ end
+ device pnp 2e.7 on
+ irq 0x25 = 0x11
+ irq 0x26 = 0x04
+ irq 0x28 = 0x81
+ irq 0x2a = 0x0d
+ irq 0x2c = 0x01
+ io 0x60 = 0x0000
+ io 0x62 = 0x0a00
+ io 0x64 = 0x0000
+ irq 0x70 = 0x00
+ irq 0x71 = 0x09
+ irq 0x72 = 0x20
+ irq 0x73 = 0x38
+ irq 0xb8 = 0x11
+ irq 0xbc = 0xc0
+ irq 0xbd = 0x03
+ irq 0xc0 = 0x01
+ irq 0xc1 = 0x04
+ irq 0xc3 = 0x41
+ irq 0xc8 = 0x01
+ irq 0xc9 = 0x04
+ irq 0xcb = 0x01
+ irq 0xe9 = 0x07
+ irq 0xf0 = 0x10
+ irq 0xf4 = 0x0c
+ irq 0xf6 = 0x0e
+ irq 0xf8 = 0x08
+ irq 0xf9 = 0x02
+ irq 0xfc = 0x7c
+ end
+ device pnp 2e.8 on
+ io 0x60 = 0x0270
+ irq 0x70 = 0x08
+ end
+ device pnp 2e.a off end
+ end
+ chip drivers/pc80/tpm
+ device pnp c31.0 on end
+ end
+ end
+ device ref pmc on end
+ device ref hda on end
+ device ref smbus on end
+ device ref gbe on end # USB_LAN (Maps to PCIe Root Port 5)
+ end
+end
diff --git a/src/mainboard/lenovo/thinkcentre_m710s/dsdt.asl b/src/mainboard/lenovo/thinkcentre_m710s/dsdt.asl
new file mode 100644
index 0000000..184fee0
--- /dev/null
+++ b/src/mainboard/lenovo/thinkcentre_m710s/dsdt.asl
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ ACPI_DSDT_REV_2,
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20110725
+)
+{
+ #include <acpi/dsdt_top.asl>
+
+ #include <cpu/intel/common/acpi/cpu.asl>
+ #include <soc/intel/common/block/acpi/acpi/platform.asl>
+ #include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+
+ Device (\_SB.PCI0) {
+ #include <soc/intel/skylake/acpi/systemagent.asl>
+ #include <soc/intel/skylake/acpi/pch.asl>
+ }
+
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/lenovo/thinkcentre_m710s/early_init.c b/src/mainboard/lenovo/thinkcentre_m710s/early_init.c
new file mode 100644
index 0000000..3c81c80
--- /dev/null
+++ b/src/mainboard/lenovo/thinkcentre_m710s/early_init.c
@@ -0,0 +1,14 @@
+
+#include <bootblock_common.h>
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8728f/it8728f.h>
+
+#define SERIAL_DEV PNP_DEV(0x2e, IT8728F_SP1)
+#define GPIO_DEV PNP_DEV(0x2e, IT8728F_GPIO)
+
+void bootblock_mainboard_early_init(void)
+{
+ ite_reg_write(GPIO_DEV, 0x23, 0x49);
+ ite_reg_write(GPIO_DEV, 0x71, 0x09);
+ ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+}
diff --git a/src/mainboard/lenovo/thinkcentre_m710s/gma-mainboard.ads b/src/mainboard/lenovo/thinkcentre_m710s/gma-mainboard.ads
new file mode 100644
index 0000000..36094f5
--- /dev/null
+++ b/src/mainboard/lenovo/thinkcentre_m710s/gma-mainboard.ads
@@ -0,0 +1,18 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ -- TODO
+ ports : constant Port_List :=
+ (DP1,
+ DP2,
+ DP3,
+ others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/lenovo/thinkcentre_m710s/gpio.h b/src/mainboard/lenovo/thinkcentre_m710s/gpio.h
new file mode 100644
index 0000000..1cd7d25
--- /dev/null
+++ b/src/mainboard/lenovo/thinkcentre_m710s/gpio.h
@@ -0,0 +1,244 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef CFG_GPIO_H
+#define CFG_GPIO_H
+
+#include <gpio.h>
+
+/* Pad configuration was generated automatically using intelp2m utility */
+static const struct pad_config gpio_table[] = {
+
+ /* ------- GPIO Community 0 ------- */
+
+ /* ------- GPIO Group GPP_A ------- */
+ _PAD_CFG_STRUCT(GPP_A0, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+ _PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K)),
+ _PAD_CFG_STRUCT(GPP_A2, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K)),
+ _PAD_CFG_STRUCT(GPP_A3, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K)),
+ _PAD_CFG_STRUCT(GPP_A4, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K)),
+ _PAD_CFG_STRUCT(GPP_A5, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+ _PAD_CFG_STRUCT(GPP_A6, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), 0),
+ _PAD_CFG_STRUCT(GPP_A7, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), 0),
+ _PAD_CFG_STRUCT(GPP_A8, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
+ _PAD_CFG_STRUCT(GPP_A9, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_PULL(DN_20K)),
+ _PAD_CFG_STRUCT(GPP_A10, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_PULL(DN_20K)),
+ _PAD_CFG_STRUCT(GPP_A11, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+ PAD_CFG_GPO(GPP_A12, 1, PLTRST),
+ _PAD_CFG_STRUCT(GPP_A13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+ _PAD_CFG_STRUCT(GPP_A14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ _PAD_CFG_STRUCT(GPP_A15, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)),
+ PAD_NC(GPP_A16, NONE),
+ PAD_NC(GPP_A17, NONE),
+ PAD_NC(GPP_A18, NONE),
+ PAD_NC(GPP_A19, NONE),
+ PAD_CFG_GPO(GPP_A20, 1, PLTRST),
+ PAD_NC(GPP_A21, NONE),
+ PAD_NC(GPP_A22, NONE),
+ PAD_CFG_GPO(GPP_A23, 1, PLTRST),
+
+ /* ------- GPIO Group GPP_B ------- */
+ _PAD_CFG_STRUCT(GPP_B0, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+ PAD_CFG_GPI_TRIG_OWN(GPP_B1, NONE, PLTRST, OFF, ACPI),
+ _PAD_CFG_STRUCT(GPP_B2, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+ PAD_NC(GPP_B3, NONE),
+ _PAD_CFG_STRUCT(GPP_B4, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+ _PAD_CFG_STRUCT(GPP_B5, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+ _PAD_CFG_STRUCT(GPP_B6, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+ _PAD_CFG_STRUCT(GPP_B7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
+ PAD_NC(GPP_B8, NONE),
+ PAD_NC(GPP_B9, NONE),
+ PAD_CFG_GPI_TRIG_OWN(GPP_B10, NONE, PLTRST, OFF, ACPI),
+ PAD_CFG_GPO(GPP_B11, 0, DEEP),
+ PAD_CFG_GPO(GPP_B12, 1, DEEP),
+ _PAD_CFG_STRUCT(GPP_B13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+ _PAD_CFG_STRUCT(GPP_B14, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_PULL(DN_20K)),
+ PAD_NC(GPP_B15, NONE),
+ PAD_NC(GPP_B16, NONE),
+ PAD_NC(GPP_B17, NONE),
+ _PAD_CFG_STRUCT(GPP_B18, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
+ PAD_NC(GPP_B19, NONE),
+ _PAD_CFG_STRUCT(GPP_B20, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+ _PAD_CFG_STRUCT(GPP_B21, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+ _PAD_CFG_STRUCT(GPP_B22, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
+ _PAD_CFG_STRUCT(GPP_B23, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(DN_20K)),
+
+ /* ------- GPIO Community 1 ------- */
+
+ /* ------- GPIO Group GPP_C ------- */
+ _PAD_CFG_STRUCT(GPP_C0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+ _PAD_CFG_STRUCT(GPP_C1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+ _PAD_CFG_STRUCT(GPP_C2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0),
+ _PAD_CFG_STRUCT(GPP_C3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+ _PAD_CFG_STRUCT(GPP_C4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+ PAD_CFG_GPI_TRIG_OWN(GPP_C5, DN_20K, DEEP, OFF, ACPI),
+ /* GPP_C6 - RESERVED */
+ /* GPP_C7 - RESERVED */
+ PAD_NC(GPP_C8, NONE),
+ PAD_NC(GPP_C9, NONE),
+ PAD_NC(GPP_C10, NONE),
+ PAD_NC(GPP_C11, NONE),
+ PAD_CFG_GPO(GPP_C12, 1, PLTRST),
+ PAD_CFG_GPO(GPP_C13, 0, PLTRST),
+ _PAD_CFG_STRUCT(GPP_C14, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+ _PAD_CFG_STRUCT(GPP_C15, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+ PAD_NC(GPP_C16, NONE),
+ PAD_NC(GPP_C17, NONE),
+ PAD_NC(GPP_C18, NONE),
+ PAD_NC(GPP_C19, NONE),
+ PAD_NC(GPP_C20, NONE),
+ PAD_NC(GPP_C21, NONE),
+ PAD_NC(GPP_C22, NONE),
+ PAD_NC(GPP_C23, NONE),
+
+ /* ------- GPIO Group GPP_D ------- */
+ PAD_NC(GPP_D0, NONE),
+ PAD_NC(GPP_D1, NONE),
+ PAD_CFG_GPI_TRIG_OWN(GPP_D2, NONE, PLTRST, OFF, ACPI),
+ PAD_CFG_GPI_TRIG_OWN(GPP_D3, NONE, PLTRST, OFF, ACPI),
+ PAD_NC(GPP_D4, NONE),
+ PAD_NC(GPP_D5, NONE),
+ PAD_NC(GPP_D6, NONE),
+ PAD_NC(GPP_D7, NONE),
+ PAD_NC(GPP_D8, NONE),
+ PAD_NC(GPP_D9, NONE),
+ PAD_NC(GPP_D10, NONE),
+ PAD_NC(GPP_D11, NONE),
+ PAD_NC(GPP_D12, NONE),
+ PAD_NC(GPP_D13, NONE),
+ PAD_CFG_GPO(GPP_D14, 0, PLTRST),
+ PAD_NC(GPP_D15, NONE),
+ _PAD_CFG_STRUCT(GPP_D16, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+ PAD_NC(GPP_D17, NONE),
+ PAD_NC(GPP_D18, NONE),
+ PAD_NC(GPP_D19, NONE),
+ PAD_NC(GPP_D20, NONE),
+ PAD_NC(GPP_D21, NONE),
+ PAD_NC(GPP_D22, NONE),
+ PAD_NC(GPP_D23, NONE),
+
+ /* ------- GPIO Group GPP_E ------- */
+ PAD_NC(GPP_E0, NONE),
+ PAD_NC(GPP_E1, NONE),
+ PAD_NC(GPP_E2, NONE),
+ PAD_NC(GPP_E3, NONE),
+ PAD_NC(GPP_E4, NONE),
+ PAD_NC(GPP_E5, NONE),
+ PAD_NC(GPP_E6, NONE),
+ PAD_NC(GPP_E7, NONE),
+ _PAD_CFG_STRUCT(GPP_E8, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+ _PAD_CFG_STRUCT(GPP_E9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+ _PAD_CFG_STRUCT(GPP_E10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+ _PAD_CFG_STRUCT(GPP_E11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+ PAD_CFG_GPO(GPP_E12, 1, DEEP),
+
+ /* ------- GPIO Group GPP_F ------- */
+ PAD_NC(GPP_F0, NONE),
+ PAD_NC(GPP_F1, NONE),
+ PAD_NC(GPP_F2, NONE),
+ PAD_NC(GPP_F3, NONE),
+ PAD_NC(GPP_F4, NONE),
+ PAD_NC(GPP_F5, NONE),
+ PAD_NC(GPP_F6, NONE),
+ PAD_NC(GPP_F7, NONE),
+ PAD_NC(GPP_F8, NONE),
+ PAD_NC(GPP_F9, NONE),
+ _PAD_CFG_STRUCT(GPP_F10, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+ _PAD_CFG_STRUCT(GPP_F11, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+ _PAD_CFG_STRUCT(GPP_F12, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+ PAD_CFG_GPI_APIC_HIGH(GPP_F13, NONE, PLTRST),
+ PAD_CFG_GPI_APIC_LOW(GPP_F14, NONE, DEEP),
+ _PAD_CFG_STRUCT(GPP_F15, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+ _PAD_CFG_STRUCT(GPP_F16, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+ _PAD_CFG_STRUCT(GPP_F17, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+ _PAD_CFG_STRUCT(GPP_F18, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0),
+ PAD_NC(GPP_F19, NONE),
+ PAD_NC(GPP_F20, NONE),
+ PAD_NC(GPP_F21, NONE),
+ PAD_CFG_GPO(GPP_F22, 1, PLTRST),
+ PAD_NC(GPP_F23, NONE),
+
+ /* ------- GPIO Group GPP_G ------- */
+ PAD_CFG_GPI_TRIG_OWN(GPP_G0, NONE, PLTRST, OFF, ACPI),
+ PAD_CFG_GPI_TRIG_OWN(GPP_G1, NONE, PLTRST, OFF, ACPI),
+ PAD_CFG_GPI_TRIG_OWN(GPP_G2, NONE, PLTRST, OFF, ACPI),
+ PAD_CFG_GPI_TRIG_OWN(GPP_G3, NONE, PLTRST, OFF, ACPI),
+ _PAD_CFG_STRUCT(GPP_G4, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+ _PAD_CFG_STRUCT(GPP_G5, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+ PAD_NC(GPP_G6, NONE),
+ PAD_NC(GPP_G7, NONE),
+ _PAD_CFG_STRUCT(GPP_G8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ _PAD_CFG_STRUCT(GPP_G9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ _PAD_CFG_STRUCT(GPP_G10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ _PAD_CFG_STRUCT(GPP_G11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+ PAD_NC(GPP_G12, NONE),
+ PAD_NC(GPP_G13, NONE),
+ PAD_NC(GPP_G14, NONE),
+ PAD_NC(GPP_G15, NONE),
+ PAD_NC(GPP_G16, NONE),
+ PAD_NC(GPP_G17, NONE),
+ PAD_NC(GPP_G18, NONE),
+ PAD_NC(GPP_G19, NONE),
+ PAD_CFG_GPO(GPP_G20, 1, PLTRST),
+ _PAD_CFG_STRUCT(GPP_G21, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+ _PAD_CFG_STRUCT(GPP_G22, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+ _PAD_CFG_STRUCT(GPP_G23, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+
+ /* ------- GPIO Group GPP_H ------- */
+ _PAD_CFG_STRUCT(GPP_H0, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
+ PAD_CFG_GPI_TRIG_OWN(GPP_H1, NONE, PLTRST, OFF, ACPI),
+ PAD_CFG_GPI_TRIG_OWN(GPP_H2, NONE, PLTRST, OFF, ACPI),
+ _PAD_CFG_STRUCT(GPP_H3, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
+ PAD_CFG_GPO(GPP_H4, 1, PLTRST),
+ PAD_NC(GPP_H5, NONE),
+ PAD_NC(GPP_H6, NONE),
+ PAD_NC(GPP_H7, NONE),
+ PAD_NC(GPP_H8, NONE),
+ PAD_NC(GPP_H9, NONE),
+ PAD_CFG_GPO(GPP_H10, 1, PLTRST),
+ PAD_CFG_GPO(GPP_H11, 1, PLTRST),
+ PAD_CFG_GPO(GPP_H12, 1, PLTRST),
+ _PAD_CFG_STRUCT(GPP_H13, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+ PAD_NC(GPP_H14, NONE),
+ PAD_NC(GPP_H15, NONE),
+ PAD_NC(GPP_H16, NONE),
+ PAD_NC(GPP_H17, NONE),
+ PAD_NC(GPP_H18, NONE),
+ PAD_NC(GPP_H19, NONE),
+ _PAD_CFG_STRUCT(GPP_H20, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+ PAD_CFG_GPI_TRIG_OWN(GPP_H21, NONE, PLTRST, OFF, ACPI),
+ PAD_CFG_GPI_TRIG_OWN(GPP_H22, NONE, PLTRST, OFF, ACPI),
+ _PAD_CFG_STRUCT(GPP_H23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+
+ /* ------- GPIO Community 2 ------- */
+
+ /* -------- GPIO Group GPD -------- */
+ _PAD_CFG_STRUCT(GPD0, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+ _PAD_CFG_STRUCT(GPD1, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+ _PAD_CFG_STRUCT(GPD2, PAD_FUNC(NF1) | PAD_IRQ_ROUTE(SCI) | PAD_BUF(RX_DISABLE) | (1 << 1), PAD_PULL(NATIVE)),
+ _PAD_CFG_STRUCT(GPD3, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)),
+ _PAD_CFG_STRUCT(GPD4, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+ _PAD_CFG_STRUCT(GPD5, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+ _PAD_CFG_STRUCT(GPD6, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+ PAD_CFG_GPO(GPD7, 1, PWROK),
+ _PAD_CFG_STRUCT(GPD8, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+ _PAD_CFG_STRUCT(GPD9, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+ _PAD_CFG_STRUCT(GPD10, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+ PAD_CFG_GPO(GPD11, 1, PWROK),
+
+ /* ------- GPIO Community 3 ------- */
+
+ /* ------- GPIO Group GPP_I ------- */
+ _PAD_CFG_STRUCT(GPP_I0, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+ _PAD_CFG_STRUCT(GPP_I1, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
+ _PAD_CFG_STRUCT(GPP_I2, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
+ _PAD_CFG_STRUCT(GPP_I3, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
+ _PAD_CFG_STRUCT(GPP_I4, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
+ PAD_CFG_GPO(GPP_I5, 1, PLTRST),
+ _PAD_CFG_STRUCT(GPP_I6, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(DN_20K)),
+ _PAD_CFG_STRUCT(GPP_I7, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+ _PAD_CFG_STRUCT(GPP_I8, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(DN_20K)),
+ _PAD_CFG_STRUCT(GPP_I9, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+ _PAD_CFG_STRUCT(GPP_I10, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(DN_20K)),
+};
+
+#endif /* CFG_GPIO_H */
diff --git a/src/mainboard/lenovo/thinkcentre_m710s/hda_verb.c b/src/mainboard/lenovo/thinkcentre_m710s/hda_verb.c
new file mode 100644
index 0000000..dc009fb
--- /dev/null
+++ b/src/mainboard/lenovo/thinkcentre_m710s/hda_verb.c
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x10ec0662, // Vendor/Device ID: Realtek ACL662
+ 0x17aa3102, // Subsystem ID
+ 12,
+ AZALIA_SUBVENDOR(0, 0x17aa3102),
+ AZALIA_PIN_CFG(0, 0x12, 0x40000000),
+ AZALIA_PIN_CFG(0, 0x14, 0x01014010),
+ AZALIA_PIN_CFG(0, 0x15, 0x90170120),
+ AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x18, 0x01a19030),
+ AZALIA_PIN_CFG(0, 0x19, 0x02a11040),
+ AZALIA_PIN_CFG(0, 0x1a, 0x0181303f),
+ AZALIA_PIN_CFG(0, 0x1b, 0x0221101f),
+ AZALIA_PIN_CFG(0, 0x1c, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x1d, 0x4047c62b),
+ AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+
+ 0x8086280b, // Vendor/Device ID: Intel HDMI
+ 0x80860101, // Subsystem ID
+ 4,
+ AZALIA_SUBVENDOR(2, 0x80860101),
+ AZALIA_PIN_CFG(2, 0x05, 0x58560010),
+ AZALIA_PIN_CFG(2, 0x06, 0x18560020),
+ AZALIA_PIN_CFG(2, 0x07, 0x18560030),
+};
+
+const u32 pc_beep_verbs[] = {};
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/lenovo/thinkcentre_m710s/romstage.c b/src/mainboard/lenovo/thinkcentre_m710s/romstage.c
new file mode 100644
index 0000000..65cd625
--- /dev/null
+++ b/src/mainboard/lenovo/thinkcentre_m710s/romstage.c
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <assert.h>
+#include <stdint.h>
+#include <string.h>
+
+#include <soc/romstage.h>
+#include <spd_bin.h>
+
+const u16 rcomp_resistors[] = {121, 75, 100};
+const u16 rcomp_targets[] = {50, 26, 20, 20, 26};
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+ FSP_M_CONFIG *const mem_cfg = &mupd->FspmConfig;
+
+ assert(sizeof(mem_cfg->RcompResistor) == sizeof(rcomp_resistors));
+ assert(sizeof(mem_cfg->RcompTarget) == sizeof(rcomp_targets));
+
+ mem_cfg->DqPinsInterleaved = 1;
+ mem_cfg->CaVrefConfig = 2;
+
+ struct spd_block blk = {
+ .addr_map = {0x50, 0x51, 0x52, 0x53},
+ };
+
+ get_spd_smbus(&blk);
+ mem_cfg->MemorySpdDataLen = blk.len;
+ mem_cfg->MemorySpdPtr00 = (uintptr_t) blk.spd_array[0];
+ mem_cfg->MemorySpdPtr01 = (uintptr_t) blk.spd_array[1];
+ mem_cfg->MemorySpdPtr10 = (uintptr_t) blk.spd_array[2];
+ mem_cfg->MemorySpdPtr11 = (uintptr_t) blk.spd_array[3];
+ dump_spd_info(&blk);
+
+ memcpy(mem_cfg->RcompResistor, rcomp_resistors, sizeof(mem_cfg->RcompResistor));
+ memcpy(mem_cfg->RcompTarget, rcomp_targets, sizeof(mem_cfg->RcompTarget));
+}
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