Marc Jones (marc@marcjonesconsulting.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17145
-gerrit
commit de970cb271a8765f1ed5b36fa1878d31202c1247 Author: Marshall Dawson marshalldawson3rd@gmail.com Date: Sat Oct 8 09:12:27 2016 -0600
northbridge/amd: Modify 00670F00 chip.h to match DCT
The Stoney device supports only a single channel of DRAM with two DIMMs. Correct the dimmensions of the SPD lookup array.
Original-Signed-off-by: Marshall Dawson marshalldawson3rd@gmail.com Original-Reviewed-by: marcj303@gmail.com (cherry picked from commit 54a5e4a7092b77cca90894e86387f719fa3aa2c8)
Change-Id: Ib776133e411d483bb5b7e3c070199befc631d209 Signed-off-by: Marc Jones marcj303@gmail.com --- src/northbridge/amd/pi/00670F00/chip.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/northbridge/amd/pi/00670F00/chip.h b/src/northbridge/amd/pi/00670F00/chip.h index 917bc65..d11d7a4 100644 --- a/src/northbridge/amd/pi/00670F00/chip.h +++ b/src/northbridge/amd/pi/00670F00/chip.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Sage Electronic Engineering, LLC + * Copyright (C) 2016 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,7 +19,7 @@
struct northbridge_amd_pi_00670F00_config { - u8 spdAddrLookup[2][2][4]; + u8 spdAddrLookup[1][1][2]; };
#endif