Arthur Heymans has uploaded this change for review.

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sb/intel/common: Add the option for static PIC routes

Recent SOC don't feature the option to reconfigure APIC to PIC routes,
hence provide to provide the PIC IRQ's directly with a soc callback
function.

Change-Id: Iebb791ec3788a792240d247313ddcfaa609269c4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
---
M src/southbridge/intel/common/Kconfig
M src/southbridge/intel/common/acpi_pirq_gen.c
M src/southbridge/intel/common/acpi_pirq_gen.h
3 files changed, 21 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/36436/1

diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig
index 31039b6..aaced43 100644
--- a/src/southbridge/intel/common/Kconfig
+++ b/src/southbridge/intel/common/Kconfig
@@ -25,6 +25,12 @@
 config SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN
 	def_bool n
 
+config SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN_STATIC_PIC_MAP
+	def_bool n
+	help
+	  Select this if the mapping of ACPI PIRQ to PIC IRQ
+	  numbers is static.
+
 config SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ
 	def_bool n
 	select SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN
diff --git a/src/southbridge/intel/common/acpi_pirq_gen.c b/src/southbridge/intel/common/acpi_pirq_gen.c
index ade1a98..ddf7609 100644
--- a/src/southbridge/intel/common/acpi_pirq_gen.c
+++ b/src/southbridge/intel/common/acpi_pirq_gen.c
@@ -72,11 +72,19 @@
 				acpigen_write_zero();
 				acpigen_write_dword(16 + pirq - PIRQ_A);
 			} else {
-				snprintf(buffer, sizeof(buffer),
-					"%s.LNK%c",
-					lpcb_path, 'A' + pirq - PIRQ_A);
-				acpigen_emit_namestring(buffer);
-				acpigen_write_dword(0);
+				/* IRQ larger than PIRQ_H are not mapped to legacy PIC */
+				if (pirq > PIRQ_H)
+					continue;
+				if (CONFIG(SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN_STATIC_PIC_MAP)) {
+					acpigen_write_zero();
+					acpigen_write_dword(intel_common_map_pic(pirq));
+				} else {
+					snprintf(buffer, sizeof(buffer),
+						 "%s.LNK%c",
+						 lpcb_path, 'A' + pirq - PIRQ_A);
+					acpigen_emit_namestring(buffer);
+					acpigen_write_dword(0);
+				}
 			}
 			acpigen_pop_len();
 		}
@@ -91,7 +99,7 @@
 
 	printk(BIOS_DEBUG, "Generating ACPI PIRQ entries\n");
 
-	if (!lpcb_path) {
+	if (!lpcb_path && !CONFIG(SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN_STATIC_PIC_MAP)) {
 		printk(BIOS_ERR, "ACPI_PIRQ_GEN: Missing LPCB ACPI path\n");
 		return;
 	}
diff --git a/src/southbridge/intel/common/acpi_pirq_gen.h b/src/southbridge/intel/common/acpi_pirq_gen.h
index 9fdee1a..6c3ceda 100644
--- a/src/southbridge/intel/common/acpi_pirq_gen.h
+++ b/src/southbridge/intel/common/acpi_pirq_gen.h
@@ -39,5 +39,6 @@
 void intel_acpi_gen_def_acpi_pirq(struct device *dev);
 enum pirq intel_common_map_pirq(const struct device *dev,
 				const enum pci_pin pci_pin);
+int intel_common_map_pic(enum pirq pirq);
 
 #endif

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